loglib

/*______________________________________________________________*/
/*								*/
/* LOG Library	: zilog.def					*/
/* SCM Library	: zilog.ddb					*/
/*								*/
/* Author	: Bartels System				*/
/* Last Revision: 97/04/15					*/
/*______________________________________________________________*/
/*								*/
/* This library includes circuit families manufactured by	*/
/* Zilog such as						*/
/*								*/
/*	- Z80 Microprocessor and Peripherals			*/
/*								*/
/* NOTE:							*/
/*								*/
/* The part names used in this library DO NOT include suffixes	*/
/* referring to temperature range, timing constraints, plastic	*/
/* or ceramic DIL packages (as long as pin compatibility is	*/
/* maintained).							*/
/*______________________________________________________________*/

/*______________________________________________________________*/
/* Z-80 CPU and Peripherals */

part z80 : dil40 {
	newattr "$comment" = "Z80 Microprocessor" ;
	newattr "$commentge" = "Z80 Mikroprozessor" ;
	newattr "$type" = "Z80" ;
	newattr "$manufacturer" = "Zilog" ;
	pin (a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,
	     d0,d1,d2,d3,d4,d5,d6,d7,
	     ck,wt,m1,mr,io,rd,wr,rf,hl,in,nm,rs,br,ba) ;
	net "vcc" : (11) ;
	net "vss" : (29) ;
	xlat (a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,
	      d0,d1,d2,d3,d4,d5,d6,d7,
	      ck,wt,mr,io,rd,wr,m1,rf,hl,in,nm,rs,br,ba)
	  to (30,31,32,33,34,35,36,37,38,39, 40,  1,  2,  3,  4,  5,
	      14,15,12, 8, 7, 9,10,13,
	       6,24,19,20,21,22,27,28,18,16,17,26,25,23) ;
	}

part z80cpu : dil40 {
	newattr "$comment" = "Z80 Microprocessor" ;
	newattr "$commentge" = "Z80 Mikroprozessor" ;
	newattr "$type" = "Z80" ;
	newattr "$manufacturer" = "Zilog" ;
	pin (6,16,17,18,19,20,21,22,23,24,25,26,27,28) ;
	bus (abus) ;
	bus (dbus) ;
	xlat (dbus.d0,dbus.d1,dbus.d2,dbus.d3,
	      dbus.d4,dbus.d5,dbus.d6,dbus.d7)
	  to (     14,     15,     12,      8,
	            7,      9,     10,     13) ;
	net "vcc" : (11) ;
	net "vss" : (29) ;
	xlat ( abus.a0, abus.a1, abus.a2, abus.a3,
	       abus.a4, abus.a5, abus.a6, abus.a7,
	       abus.a8, abus.a9,abus.a10,abus.a11,
	      abus.a12,abus.a13,abus.a14,abus.a15)
	  to (      30,      31,      32,      33,
	            34,      35,      36,      37,
	            38,      39,      40,       1,
	             2,       3,       4,       5) ;
	}

part z80ctc : dil28b {
	newattr "$comment" = "Z80 Controller" ;
	newattr "$commentge" = "Z80-Controller" ;
	newattr "$type" = "Z80 CTC" ;
	newattr "$manufacturer" = "Zilog" ;
	net "+5v" : (24) ;
	net "gnd" : (5) ;
	bus (dbus) ;
	xlat (dbus.d0,dbus.d1,dbus.d2,dbus.d3,
	      dbus.d4,dbus.d5,dbus.d6,dbus.d7)
	  to (     25,     26,     27,     28,
	            1,      2,      3,      4) ;
	xlat (16,18,19,14,10,6,13,11,12,15,23,7,22,8,21,9,20,17)
	  to (16,18,19,14,10,6,13,11,12,15,23,7,22,8,21,9,20,17) ;
	}

part z80dma : dil40 {
	newattr "$comment" = "Z80 Direct Memory Access" ;
	newattr "$commentge" = "Z80-Speicherzugriffsbaustein" ;
	newattr "$type" = "Z80 DMA" ;
	newattr "$manufacturer" = "Zilog" ;
	net "+5v" : (11) ;
	net "gnd" : (30) ;
	bus (dbus) ;
	xlat (dbus.d0,dbus.d1,dbus.d2,dbus.d3,
	      dbus.d4,dbus.d5,dbus.d6,dbus.d7)
	  to (     35,     34,     33,     32,
	           31,     29,     28,     27) ;
	bus (abus) ;
	xlat ( abus.a0, abus.a1, abus.a2, abus.a3,
	       abus.a4, abus.a5, abus.a6, abus.a7,
	       abus.a8, abus.a9,abus.a10,abus.a11,
	      abus.a12,abus.a13,abus.a14,abus.a15)
	  to (       6,       5,       4,       3,
	             2,       1,      40,      39,
	            24,      23,      22,      21,
	            20,      19,      18,      17) ;
	xlat (15,14,13,26,10,12,9,8,7,25,16,37,38,36)
	  to (15,14,13,26,10,12,9,8,7,25,16,37,38,36) ;
	}

part z80pio : dil40 {
	newattr "$comment" = "Z80 Parallel Interface" ;
	newattr "$commentge" = "Z80 Parallel-Schnittstelle" ;
	newattr "$type" = "Z80 PIO" ;
	newattr "$manufacturer" = "Zilog" ;
	pin (a0,a1,d0,d1,d2,d3,d4,d5,d6,d7,
	     ce,rd,rq,ck,m1,in,ei,eo,
	     p0,p1,p2,p3,p4,p5,p6,p7,ps,pr,
	     q0,q1,q2,q3,q4,q5,q6,q7,qs,qr) ;
	net "vcc" : (26) ;
	net "vss" : (11) ;
	xlat (a0,a1,d0,d1,d2,d3,d4,d5,d6,d7,
	      ce,rd,rq,ck,m1,in,ei,eo,
	      p0,p1,p2,p3,p4,p5,p6,p7,ps,pr,
	      q0,q1,q2,q3,q4,q5,q6,q7,qs,qr)
	  to ( 5, 6,19,20, 1,40,39,38, 3, 2,
	       4,35,36,25,37,23,24,22,
	      15,14,13,12,10, 9, 8, 7,16,18,
	      27,28,29,30,31,32,33,34,17,21) ;
	}

part z80pio_ : dil40 {
	newattr "$comment" = "Z80 Parallel Interface" ;
	newattr "$commentge" = "Z80 Parallel-Schnittstelle" ;
	newattr "$type" = "Z80 PIO" ;
	newattr "$manufacturer" = "Zilog" ;
	pin (4,5,6,7,8,9,10,12,13,14,15,16,17,18,21,22,23,24,25,
	     27,28,29,30,31,32,33,34,35,36,37) ;
	bus (dbus) ;
	xlat (dbus.d0,dbus.d1,dbus.d2,dbus.d3,
	      dbus.d4,dbus.d5,dbus.d6,dbus.d7)
	  to (     19,     20,      1,     40,
	           39,     38,      3,      2) ;
	net "vcc" : (26) ;
	net "vss" : (11) ;
	}

part z80sio : dil40 {
	newattr "$comment" = "Z80 Serial I/O" ;
	newattr "$commentge" = "Z80 Serielle Schnittstelle" ;
	newattr "$type" = "Z80 SIO" ;
	newattr "$manufacturer" = "Zilog" ;
	pin ( 5, 6, 7, 8,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,
	     26,27,28,29,30,32,33,34,35,36) ;
	bus (dbus) ;
	xlat (dbus.d0,dbus.d1,dbus.d2,dbus.d3,
	      dbus.d4,dbus.d5,dbus.d6,dbus.d7)
	  to (     40,      1,     39,      2,
	           38,      3,     37,      4) ;
	net "vcc" : (9) ;
	net "vss" : (31) ;
	}

/*______________________________________________________________*/
/* Logical Library definition file end */

end.