loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d74s.def                                  */
/* SCM Library   : d74s.ddb                                  */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - Bipolar TTL Schottky / Series 74S                       */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 74  = Commercial (0..70 Degree Celcius)   */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 74s00 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s02 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74s03 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s04 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74s05 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74s08 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s09 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s10 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74s11 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74s15 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74s20 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74s22 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74s30 : default so14,dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 74s32 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s37 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s38 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s40 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74s51 : default so14,dil14 {
	newattr "$comment" = "Dual 2 Wide 2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b,c, d,y)
	  to (1,13,9,10,8)
	  or (2, 3,4, 5,6) ;
	swap ( [  (( 1,13)), (( 9,10)), 8 ],
	       [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 74s64 : default so14,dil14 {
	newattr "$comment" = "4-2-3-2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,k,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d, e,f,g,h,i,j,k,y)
	  to (9,10,11,12,13,1,2,3,4,5,6,8) ;
	swap internal ( (( 9,10)), (( 2, 3)) ) ;
	swap internal ( ((11,12,13, 1)) ) ;
	swap internal ( (( 4, 5, 6)) ) ;
	}

part 74s65 : default so14,dil14 {
	newattr "$comment" = "4-2-3-2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,d,e,f,g,h,i,j,k,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d, e,f,g,h,i,j,k,y)
	  to (9,10,11,12,13,1,2,3,4,5,6,8) ;
	swap internal ( (( 9,10)), (( 2, 3)) ) ;
	swap internal ( ((11,12,13, 1)) ) ;
	swap internal ( (( 4, 5, 6)) ) ;
	}

part 74s74 : default so14,dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 74s85 : default so16,dil16 {
	newattr "$comment" = "4 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q")
	  to (10,12,13,15, 9,11,14, 1,    2,    3,    4,    7,    6,    5) ;
	swap internal ( (10,12,13,15, 2, 7), ( 9,11,14, 1, 4, 5) ) ;
	}

part 74s86 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s112 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   4, 3,  1, 2,  15,5, 6)
	  or (  10,11, 13,12,  14,9, 7) ;
	swap ( ( 4, 3, 1, 2,15, 5, 6), (10,11,13,12,14, 9, 7) ) ;
	}

part 74s113 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre, j,clk, k,q,/q)
	  to (   4, 3,  1, 2,5, 6)
	  or (  10,11, 13,12,9, 8) ;
	swap ( ( 4, 3, 1, 2, 5, 6), (10,11,13,12, 9, 8) ) ;
	}

part 74s114 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (   1, 13,    4, 3, 2, 5,  6,   10,11,12, 9,  8) ;
	swap ( [  1,13, ( 4, 3, 2, 5, 6), (10,11,12, 9, 8) ] ) ;
	}

part 74s124 : default so16,dil16 {
	newattr "$comment" = "Dual Voltage Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (vcc,vcclog,gnd,gndlog,/1g,1rng,1fc,1cx1,1cx2,1y,/2g,2rng,2fc,
	     2cx1,2cx2,2y) ;
	xlat (vcc,vcclog,gnd,gndlog,/1g,1rng,1fc,1cx1,1cx2,1y,/2g,2rng,2fc,
	      2cx1,2cx2,2y)
	  to ( 15,    16,  8,     9,  6,   3,  2,   4,   5, 7, 11,  14,  1,
	        12,  13,10) ;
	swap ( [ 15,16, 8, 9,
	       ( 6, 3, 2, 4, 5, 7),
	       (11,14, 1,12,13,10) ] ) ;
	}

part 74s132 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74s133 : default so16,dil16 {
	newattr "$comment" = "13 Input Positive NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,k,l,m,y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,d,e,f,g, h, i, j, k, l, m,y)
	  to (1,2,3,4,5,6,7,10,11,12,13,14,15,9) ;
	swap ( (( 1, 2, 3, 4, 5, 6, 7,10,11,12,13,14,15), 9) ) ;
	}

part 74s134 : default so16,dil16 {
	newattr "$comment" = "12 Input Positive NAND Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,a,b,c,d,e,f,g,h,i,j,k,l,y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/oc,a,b,c,d,e,f,g, h, i, j, k, l,y)
	  to ( 15,1,2,3,4,5,6,7,10,11,12,13,14,9) ;
	swap internal ( (( 1, 2, 3, 4, 5, 6, 7,10,11,12,13,14)) ) ;
	}

part 74s135 : default so16,dil16 {
	newattr "$comment" = "Quad Exclusive OR/NOR Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,1a,1b,1y,2a,2b,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( c,1a,1b,1y,2a,2b,2y)
	  to ( 4, 1, 2, 3, 5, 6, 7)
	  or (12,10,11, 9,14,15,13) ;
	swap ( [  4, (( 1, 2), 3), (( 5, 6), 7) ],
	       [ 12, ((10,11), 9), ((14,15),13) ] ) ;
	}

part 74s138 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (1,2,3, 6,   4,   5,15,14,13,12,11,10, 9, 7) ;
	swap internal ( (( 4, 5)) ) ;
	}

part 74s139 : default so16,dil16 {
	newattr "$comment" = "Dual 2 of 4 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,/g,y0,y1,y2,y3)
	  to ( 2, 3, 1, 4, 5, 6, 7)
	  or (14,13,15,12,11,10, 9) ;
	swap ( ( 2, 3, 1, 4, 5, 6, 7), (14,13,15,12,11,10, 9) ) ;
	}

part 74s140 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74s148 : default so16,dil16 {
	newattr "$comment" = "8 to 3 Octal Priority Encoder" ;
	newattr "$ttlout" = "TP" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2)
	  to (10,11,12,13, 1, 2, 3, 4, 5,15,14, 9, 7, 6) ;
	}

part 74s151 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74s153 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74s157 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74s158 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74s162 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74s163 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74s168 : default dil16 {
	newattr "$comment" = "4 Bit Decade Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74s169 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74s174 : default so16,dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,d2,q2,d3,d4,q3,q4,d5,q5,d6,q6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,d2,q2,d3,q3,d4,q4,d5,q5,d6,q6)
	  to (   1,  9, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  1, 9,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 74s175 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (   1,  9, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  1, 9,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 74s181 : default so24,dil24,dil24b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to ( 6, 5, 4, 3,8, 7,15,17,   14,    16,  2,  1,  9, 23, 22, 10,
	       21, 20, 11, 19, 18, 13) ;
	}

part 74s182 : default so16,dil16 {
	newattr "$comment" = "16 Bit Look-Ahead Carry Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	     /g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	      /g)
	  to ( 13,  4,  3,  2,  1, 15, 14,  6,  5,    12,    11,     9, 7,
	      10) ;
	}

part 74s189 : default so16,dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3)
	  to ( 1,15,14,13,  2, 3, 4,  5, 6,  7,10,  9,12, 11) ;
	}

part 74s194 : default so16,dil16 {
	newattr "$comment" = "4 Bit Universal Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd)
	  to (   1, 9,10, 11,    2,3,15,4,14,5,13,6,    7,12) ;
	}

part 74s195 : default so16,dil16 {
	newattr "$comment" = "4 Bit Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd)
	  to (   1,   9, 10,2, 3,4,15,5,14,6,13,7,12, 11) ;
	}

part 74s196 : default so14,dil14 {
	newattr "$comment" = "Presetable Decade (Bi-Quinary) Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/ld,/clr,clk1,a,qa,clk2,b,c,d,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/ld,/clr,clk1,a,qa,clk2, b,c, d,qb,qc,qd)
	  to (  1,  13,   8,4, 5,   6,10,3,11, 9, 2,12) ;
	}

part 74s197 : default so14,dil14 {
	newattr "$comment" = "Presetable 4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/ld,/clr,clk1,a,qa,clk2,b,c,d,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/ld,/clr,clk1,a,qa,clk2, b,c, d,qb,qc,qd)
	  to (  1,  13,   8,4, 5,   6,10,3,11, 9, 2,12) ;
	}

part 74s201 : default so16,dil16 {
	newattr "$comment" = "256 Bit High Performance RAM" ;
	newattr "$ttlout" = "TS" ;
	pin (a0,a1,a2,a3,a4,a5,a6,a7,/s1,/s2,/s3,rw,d,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,a4,a5,a6,a7,/s1,/s2,/s3,rw, d,/q)
	  to ( 1, 2,15, 7, 9,10,11,14,  3,  4,  5,12,13, 6) ;
	swap internal ( (( 3, 4, 5)) ) ;
	}

part 74s226 : default so16,dil16 {
	newattr "$comment" = "4 Bit Parallel Latched Bus Transceiver" ;
	pin (s1,s2,gab,gba,ocab,ocba,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (s1,s2,gab,gba,ocab,ocba,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 2,14, 15,  1,   9,   7, 3,13, 4,12, 5,11, 6,10) ;
	}

part 74s240 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74s241 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74s244 : default so20,dil20 {
	newattr "$comment" = "Octal Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74s251 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74s253 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74s257 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74s258 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74s260 : default so14,dil14 {
	newattr "$comment" = "Dual 5 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c, d, e,y)
	  to (1,2,3,12,13,5)
	  or (4,8,9,10,11,6) ;
	swap ( (( 1, 2, 3,12,13), 5), (( 4, 8, 9,10,11), 6) ) ;
	}

part 74s273 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (   1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74s280 : default so14,dil14 {
	newattr "$comment" = "9 Bit Odd/Even Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,even,odd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,even,odd)
	  to (8,9,10,11,12,13,1,2,4,   5,  6) ;
	swap ( (( 8, 9,10,11,12,13, 1, 2, 4), 5, 6) ) ;
	}

part 74s283 : default so16,dil16 {
	newattr "$comment" = "4 Bit Full Adder, Fast Carry" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4)
	  to ( 5, 3,14,12, 6, 2,15,11, 7, 4, 1,13,10, 9) ;
	swap internal ( (( 5, 6),( 3, 2),(14,15),(12,11)) ) ;
	}

part 74s289 : default so16,dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3)
	  to ( 1,15,14,13,  2, 3, 4,  5, 6,  7,10,  9,12, 11) ;
	}

part 74s299 : default so20,dil20 {
	newattr "$comment" = "8 Bit Universal PIPO Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74s301 : default so16,dil16 {
	newattr "$comment" = "256 Bit High Performance RAM" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,a2,a3,a4,a5,a6,a7,/s1,/s2,/s3,rw,d,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,a4,a5,a6,a7,/s1,/s2,/s3,rw, d,/q)
	  to ( 1, 2,15, 7, 9,10,11,14,  3,  4,  5,12,13, 6) ;
	swap internal ( (( 3, 4, 5)) ) ;
	}

part 74s373 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74s374 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74s381 : default so20,dil20 {
	newattr "$comment" = "ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,cn,/p,/g,a0,b0,f0,a1,b1,f1,a2,b2,f2,a3,b3,f3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,s2,cn,/p,/g,a0,b0,f0,a1,b1,f1,a2,b2,f2,a3,b3,f3)
	  to ( 5, 6, 7,15,14,13, 3, 4, 8, 1, 2, 9,19,18,11,17,16,12) ;
	}

part 74s436 : default so16,dil16 {
	newattr "$comment" = "Line/Memory Driver" ;
	pin (/g1,/g2,1a,1y,2a,2y,3a,3y,4a,4y,5a,5y,6a,6y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,1a,1y,2a,2y,3a,3y,4a,4y,5a,5y,6a,6y)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( (( 1,15)) ) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	}

part 74s437 : default so16,dil16 {
	newattr "$comment" = "Line/Memory Driver" ;
	pin (/g1,/g2,1a,1y,2a,2y,3a,3y,4a,4y,5a,5y,6a,6y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,1a,1y,2a,2y,3a,3y,4a,4y,5a,5y,6a,6y)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( (( 1,15)) ) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	}

part 74s484 : default so20,dil20 {
	newattr "$comment" = "BCD to Binary Converter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a,b,c,d,e,f,g,h,y1,y2,y3,y4,y5,y6,y7,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a,b,c,d,e, f, g, h,y1,y2,y3,y4,y5,y6,y7,y8)
	  to ( 15, 16,5,4,3,2,1,19,18,17, 6, 7, 8, 9,11,12,13,14) ;
	swap internal ( ((15,16)) ) ;
	}

part 74s485 : default so20,dil20 {
	newattr "$comment" = "Binary to BCD Converter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a,b,c,d,e,f,g,h,y1,y2,y3,y4,y5,y6,y7,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a,b,c,d,e, f, g, h,y1,y2,y3,y4,y5,y6,y7,y8)
	  to ( 15, 16,5,4,3,2,1,19,18,17, 6, 7, 8, 9,11,12,13,14) ;
	swap internal ( ((15,16)) ) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.