loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d74l.def                                  */
/* SCM Library   : d74l.ddb                                  */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - Bipolar TTL Low Power / Series 74L                      */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 74  = Commercial (0..70 Degree Celcius)   */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 74l00 : default dil14,so14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74l02 : default dil14,so14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74l03 : default dil14,so14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74l04 : default dil14,so14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74l10 : default dil14,so14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74l20 : default dil14,so14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74l30 : default dil14,so14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 74l42 : default dil16,so16 {
	newattr "$comment" = "BCD to Decimal Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 74l43 : default dil16,so16 {
	newattr "$comment" = "Excess-3 to Decimal Decoder" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 74l44 : default dil16,so16 {
	newattr "$comment" = "Excess-3-Gray to Decimal Decoder" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 74l46 : default dil16,so16 {
	newattr "$comment" = "BCD to 7-Segment Decoder, 30V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74l47 : default dil16,so16 {
	newattr "$comment" = "BCD to 7-Segment Decoder, 15V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74l51 : mainpart dil14,so14 {
	newattr "$comment" = "3-3/2-2 Input AND-OR-Invert Gates" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c,d, e, f,y)
	  to (1,12,13,9,10,11,8) ;
	swap ( [  (( 1,12,13)), (( 9,10,11)), 8 ] ) ;
	}

part 74l51x : subpart 74l51 {
	pin (a,b,c,d,y) ;
	xlat (a,b,c,d,y)
	  to (2,3,4,5,6) ;
	swap ( [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 74l54 : default dil14,so14 {
	newattr "$comment" = "2-3-3-2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h, i, j,y)
	  to (1,2,3,4,5,9,10,11,12,13,6) ;
	swap internal ( (( 1, 2)), ((12,13)) ) ;
	swap internal ( (( 3, 4, 5)), (( 9,10,11)) ) ;
	}

part 74l55 : default dil14,so14 {
	newattr "$comment" = "2 Wide 4 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d, e, f, g, h,y)
	  to (1,2,3,4,10,11,12,13,8) ;
	swap internal ( (( 1, 2, 3, 4)), ((10,11,12,13)) ) ;
	}

part 74l72 : default dil14,so14 {
	newattr "$comment" = "J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j1,j2,j3,clk,k1,k2,k3,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,j1,j2,j3,clk,k1,k2,k3,/clr,q,/q)
	  to (  13, 3, 4, 5, 12, 9,10,11,   2,8, 6) ;
	}

part 74l74 : default dil14,so14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 74l75 : default dil16,so16 {
	newattr "$comment" = "Quad Bistable Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (d0,d1,c,q0,/q0,q1,/q1) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (d0,d1, c,q0,/q0,q1,/q1)
	  to ( 2, 3,13,16,  1,15, 14)
	  or ( 6, 7, 4,10, 11, 9,  8) ;
	swap ( ( 2, 3,13,16, 1,15,14), ( 6, 7, 4,10,11, 9, 8) ) ;
	}

part 74l77 : default dil14,so14 {
	newattr "$comment" = "4 Bit Bistable Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (c,d0,d1,q0,q1) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat ( c,d0,d1,q0,q1)
	  to (12, 1, 2,14,13)
	  or ( 3, 5, 6, 9, 8) ;
	swap ( (12, 1,14, 2,13), ( 3, 5, 9, 6, 8) ) ;
	}

part 74l85 : default dil16,so16 {
	newattr "$comment" = "4 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q")
	  to (10,12,13,15, 9,11,14, 1,    2,    3,    4,    7,    6,    5) ;
	swap internal ( (10,12,13,15, 2, 7), ( 9,11,14, 1, 4, 5) ) ;
	}

part 74l86 : default dil14,so14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74l90 : default dil14,so14 {
	newattr "$comment" = "Decade Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,r91,r92,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02,r91,r92, a,qa,b,qb,qc,qd)
	  to (  2,  3,  6,  7,14,12,1, 9, 8,11) ;
	swap internal ( (( 2, 3)) ) ;
	swap internal ( (( 6, 7)) ) ;
	}

part 74l91 : default dil14,so14 {
	newattr "$comment" = "8 Bit Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (ck,a,b,q,/q) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (ck, a, b, q,/q)
	  to ( 9,12,11,13,14) ;
	swap internal ( ((12,11)) ) ;
	}

part 74l95 : default dil14,so14 {
	newattr "$comment" = "4 Bit Shift Register PISO" ;
	newattr "$ttlout" = "TP" ;
	pin (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd)
	  to (   6,   9,   8,  1,2,13,3,12,4,11,5,10) ;
	}

part 74l96 : default dil16,so16 {
	newattr "$comment" = "5 Bit Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,pre,ser,a,qa,b,qb,c,qc,d,qd,e,qe) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (/clr,clk,pre,ser,a,qa,b,qb,c,qc,d,qd,e,qe)
	  to (  16,  1,  8,  9,2,15,3,14,4,13,6,11,7,10) ;
	}

part 74l121 : default dil14,so14 {
	newattr "$comment" = "Monostable Multivibrator" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,b,ri,cx,rxcx,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a1,a2,b,ri,cx,rxcx,q,/q)
	  to ( 3, 4,5, 9,10,  11,6, 1) ;
	swap internal ( (( 3, 4)) ) ;
	}

part 74l122 : default dil14,so14 {
	newattr "$comment" = "Monostable Multivibrator, Retriggerable" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,b1,b2,/clr,ri,cx,rxcx,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a1,a2,b1,b2,/clr,ri,cx,rxcx,q,/q)
	  to ( 1, 2, 3, 4,   5, 9,11,  13,8, 6) ;
	swap internal ( (( 1, 2)) ) ;
	swap internal ( (( 3, 4)) ) ;
	}

part 74l123 : default dil16,so16 {
	newattr "$comment" = "Dual Monostable Multivibrator, Retrigg." ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/clr,cx,rx,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,rx, q,/q)
	  to (1, 2,   3,14,15,13, 4)
	  or (9,10,  11, 6, 7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 74l153 : default dil16,so16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74l154 : default dil24,dil24b {
	newattr "$comment" = "4 of 16 Line Decoder/Demultiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,
	     y14,y15) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat ( a, b, c, d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,
	      y13,y14,y15)
	  to (23,22,21,20, 18, 19, 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 13, 14,
	       15, 16, 17) ;
	swap internal ( ((18,19)) ) ;
	}

part 74l157 : default dil16,so16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74l165 : default so16,dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh,/qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (shld,clkinh,clk,ser, a, b, c, d,e,f,g,h,qh,/qh)
	  to (   1,    15,  2, 10,11,12,13,14,3,4,5,6, 9,  7) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.