loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d74hct.def                                */
/* SCM Library   : d74hct.ddb                                */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - High Speed CMOS with TTL Inputs / Series 74HCT          */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 74  = Commercial (-40..85 Degree Celcius) */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 74hct00 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74hct02 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74hct04 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74hct05 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74hct07 : default so14,dil14 {
	newattr "$comment" = "Hex Buffer, 30V Output" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74hct08 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74hct09 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74hct10 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74hct11 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74hct14 : default so14,dil14 {
	newattr "$comment" = "Hex Schmitt Trigger" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74hct20 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74hct21 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input AND Gate" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74hct27 : default so14,dil14 {
	newattr "$comment" = "Triple 2 Input NOR Gate" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74hct30 : default so14,dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 74hct32 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input OR Gate" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74hct34 : default so14,dil14 {
	newattr "$comment" = "Hex Buffer" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74hct35 : default so14,dil14 {
	newattr "$comment" = "Hex Buffer" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74hct42 : default so16,dil16 {
	newattr "$comment" = "BCD to Decimal Decoder" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 74hct51 : mainpart so14,dil14 {
	newattr "$comment" = "3-3/2-2 Input AND-OR-Invert Gates" ;
	pin (a,b,c,d,e,f,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c,d, e, f,y)
	  to (1,12,13,9,10,11,8) ;
	swap ( [  (( 1,12,13)), (( 9,10,11)), 8 ] ) ;
	}

part 74hct51x : subpart 74hct51 {
	pin (a,b,c,d,y) ;
	xlat (a,b,c,d,y)
	  to (2,3,4,5,6) ;
	swap ( [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 74hct58 : mainpart so14,dil14 {
	newattr "$comment" = "3-3/2-2 Input AND-OR-Invert Gates" ;
	pin (a,b,c,d,e,f,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c,d, e, f,y)
	  to (1,12,13,9,10,11,8) ;
	swap ( [  (( 1,12,13)), (( 9,10,11)), 8 ] ) ;
	}

part 74hct58x : subpart 74hct58 {
	pin (a,b,c,d,y) ;
	xlat (a,b,c,d,y)
	  to (2,3,4,5,6) ;
	swap ( [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 74hct73 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Clear" ;
	pin (j,clk,k,/clr,q,/q) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat ( j,clk, k,/clr, q,/q)
	  to (14,  1, 3,   2,12,13)
	  or ( 7,  5,10,   6, 9, 8) ;
	swap ( (14, 1, 3, 2,12,13), ( 7, 5,10, 6, 9, 8) ) ;
	}

part 74hct74 : default so14,dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 74hct75 : default so16,dil16 {
	newattr "$comment" = "Quad Bistable Latch" ;
	pin (d0,d1,c,q0,/q0,q1,/q1) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (d0,d1, c,q0,/q0,q1,/q1)
	  to ( 2, 3,13,16,  1,15, 14)
	  or ( 6, 7, 4,10, 11, 9,  8) ;
	swap ( ( 2, 3,13,16, 1,15,14), ( 6, 7, 4,10,11, 9, 8) ) ;
	}

part 74hct76 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	pin (j,k,clk,/pre,/clr,q,/q) ;
	net "vss" : (13) ;
	net "vcc" : (5) ;
	xlat (j, k,clk,/pre,/clr, q,/q)
	  to (4,16,  1,   2,   3,15,14)
	  or (9,12,  6,   7,   8,11,10) ;
	swap ( ( 4,16, 1, 2, 3,15,14), ( 9,12, 6, 7, 8,11,10) ) ;
	}

part 74hct77 : default so14,dil14 {
	newattr "$comment" = "4 Bit Bistable Latch" ;
	pin (c,d0,d1,q0,q1) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat ( c,d0,d1,q0,q1)
	  to (12, 1, 2,14,13)
	  or ( 3, 5, 6, 9, 8) ;
	swap ( (12, 1,14, 2,13), ( 3, 5, 9, 6, 8) ) ;
	}

part 74hct78 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Common Clear/Clock" ;
	pin (clk,/clr,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat (clk,/clr,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (  1,   5,    2, 3,14,13, 12,    6,10, 7, 8,  9) ;
	swap internal ( ( 2, 3,14,13,12), ( 6,10, 7, 8, 9) ) ;
	}

part 74hct80 : default so14,dil14 {
	newattr "$comment" = "Gated Full Adder" ;
	pin (cn,a1,a2,ax,ac,b1,b2,bx,bc,"/cn+1",s,/s) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (cn,a1,a2,ax,ac,b1,b2,bx,bc,"/cn+1",s,/s)
	  to ( 3, 8, 9,10,11,12,13, 1, 2,      4,5, 6) ;
	swap internal ( ( 8, 9,10,11), (12,13, 1, 2) ) ;
	}

part 74hct82 : default so14,dil14 {
	newattr "$comment" = "2 Bit Binary Full Adder" ;
	pin (ci,a1,a2,b1,b2,c2,s1,s2) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat (ci,a1,a2,b1,b2,c2,s1,s2)
	  to ( 5, 2,14, 3,13,10, 1,12) ;
	swap internal ( (( 2, 3)) ) ;
	swap internal ( ((14,13)) ) ;
	}

part 74hct83 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Full Adder, Fast Carry" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,ci,y0,y1,y2,y3,co) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,ci,y0,y1,y2,y3,co)
	  to (10, 8, 3, 1,11, 7, 4,16,13, 9, 6, 2,15,14) ;
	swap internal ( (10, 8, 3, 1), (11, 7, 4,16) ) ;
	}

part 74hct85 : default so16,dil16 {
	newattr "$comment" = "4 Bit Magnitude Comparator" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q")
	  to (10,12,13,15, 9,11,14, 1,    2,    3,    4,    7,    6,    5) ;
	swap internal ( (10,12,13,15, 2, 7), ( 9,11,14, 1, 4, 5) ) ;
	}

part 74hct86 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74hct90 : default so14,dil14 {
	newattr "$comment" = "Decade Counter" ;
	pin (r01,r02,r91,r92,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02,r91,r92, a,qa,b,qb,qc,qd)
	  to (  2,  3,  6,  7,14,12,1, 9, 8,11) ;
	swap internal ( (( 2, 3)) ) ;
	swap internal ( (( 6, 7)) ) ;
	}

part 74hct91 : default so14,dil14 {
	newattr "$comment" = "8 Bit Shift Register" ;
	pin (ck,a,b,q,/q) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (ck, a, b, q,/q)
	  to ( 9,12,11,13,14) ;
	swap internal ( ((12,11)) ) ;
	}

part 74hct93 : default so14,dil14 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	pin (r01,r02,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02, a,qa,b,qb,qc,qd)
	  to (  2,  3,14,12,1, 9, 8,11) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74hct95 : default so14,dil14 {
	newattr "$comment" = "4 Bit Shift Register PISO" ;
	pin (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd)
	  to (   6,   9,   8,  1,2,13,3,12,4,11,5,10) ;
	}

part 74hct97 : default so16,dil16 {
	newattr "$comment" = "6 Bit Binary Rate Multiplier" ;
	pin (clk,stb,ei,uc,clr,a,b,c,d,e,f,eo,y,z) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,stb,ei,uc,clr,a,b, c, d,e,f,eo,y,z)
	  to (  9, 10,11,12, 13,4,1,14,15,2,3, 7,6,5) ;
	}

part 74hct100 : default so24,dil24,dil24b {
	newattr "$comment" = "Dual 8 Bit Bistable Latch" ;
	pin (g,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (7) ;
	net "vcc" : (24) ;
	xlat ( g,d1,q1,d2,q2,d3,q3,d4,q4)
	  to (23, 2, 5, 3, 4,22,19,21,20)
	  or (12,11, 8,10, 9,15,18,16,17) ;
	swap ( [ 23, ( 2, 5), ( 3, 4), (22,19), (21,20) ],
	       [ 12, (11, 8), (10, 9), (15,18), (16,17) ] ) ;
	}

part 74hct107 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Clear" ;
	pin (j,clk,k,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (j,clk, k,/clr,q,/q)
	  to (1, 12, 4,  13,3, 2)
	  or (8,  9,11,  10,5, 6) ;
	swap ( ( 1,12, 4,13, 3, 2), ( 8, 9,11,10, 5, 6) ) ;
	}

part 74hct108 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	pin (clk,/clr,1j,1k,/1pre,1q,/1q,2j,2k,/2pre,2q,/2q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (clk,/clr,1j,1k,/1pre,1q,/1q,2j,2k,/2pre,2q,/2q)
	  to (  9,  12, 4, 1,   13, 2,  3,11, 8,   10, 6,  5) ;
	swap ( [  9,12, ( 4, 1,13, 2, 3), (11, 8,10, 6, 5) ] ) ;
	}

part 74hct109 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	pin (/pre,j,clk,/k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk,/k,/clr, q,/q)
	  to (   5, 2,  4, 3,   1, 6, 7)
	  or (  11,14, 12,13,  15,10, 9) ;
	swap ( ( 5, 2, 4, 3, 1, 6, 7), (11,14,12,13,15,10, 9) ) ;
	}

part 74hct112 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   4, 3,  1, 2,  15,5, 6)
	  or (  10,11, 13,12,  14,9, 7) ;
	swap ( ( 4, 3, 1, 2,15, 5, 6), (10,11,13,12,14, 9, 7) ) ;
	}

part 74hct113 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset" ;
	pin (/pre,j,clk,k,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre, j,clk, k,q,/q)
	  to (   4, 3,  1, 2,5, 6)
	  or (  10,11, 13,12,9, 8) ;
	swap ( ( 4, 3, 1, 2, 5, 6), (10,11,13,12, 9, 8) ) ;
	}

part 74hct114 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	pin (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (   1, 13,    4, 3, 2, 5,  6,   10,11,12, 9,  8) ;
	swap ( [  1,13, ( 4, 3, 2, 5, 6), (10,11,12, 9, 8) ] ) ;
	}

part 74hct123 : default so16,dil16 {
	newattr "$comment" = "Dual Monostable Multivibrator, Retrigg." ;
	pin (a,b,/clr,cx,rx,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,rx, q,/q)
	  to (1, 2,   3,14,15,13, 4)
	  or (9,10,  11, 6, 7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 74hct125 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 74hct126 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 74hct131 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder, Address Registers" ;
	pin (clk,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (  4,1,2,3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 74hct132 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Schmitt Trigger" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74hct137 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder, Address Registers" ;
	pin (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (  4,1,2,3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 74hct138 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder" ;
	pin (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (1,2,3, 6,   4,   5,15,14,13,12,11,10, 9, 7) ;
	swap internal ( (( 4, 5)) ) ;
	}

part 74hct139 : default so16,dil16 {
	newattr "$comment" = "Dual 2 of 4 Decoder" ;
	pin (a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,/g,y0,y1,y2,y3)
	  to ( 2, 3, 1, 4, 5, 6, 7)
	  or (14,13,15,12,11,10, 9) ;
	swap ( ( 2, 3, 1, 4, 5, 6, 7), (14,13,15,12,11,10, 9) ) ;
	}

part 74hct147 : default so16,dil16 {
	newattr "$comment" = "10-Decimal to 4-BCD Priority Encoder" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,i9,a,b,c,d) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,i9,a,b,c, d)
	  to (11,12,13, 1, 2, 3, 4, 5,10,9,7,6,14) ;
	}

part 74hct148 : default so16,dil16 {
	newattr "$comment" = "8 to 3 Octal Priority Encoder" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2)
	  to (10,11,12,13, 1, 2, 3, 4, 5,15,14, 9, 7, 6) ;
	}

part 74hct149 : default so20,dil20 {
	newattr "$comment" = "8 to 8 Priority Coder" ;
	pin (/rqe,/0,/1,/2,/3,/4,/5,/6,/7,/rqp,/q0,/q1,/q2,/q3,/q4,/q5,/q6,
	     /q7) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/rqe,/0,/1,/2,/3,/4,/5,/6,/7,/rqp,/q0,/q1,/q2,/q3,/q4,/q5,/q6,
	      /q7)
	  to (   9, 1, 2, 3, 4, 5, 6, 7, 8,  11, 19, 18, 17, 16, 15, 14, 13,
	       12) ;
	}

part 74hct151 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74hct153 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74hct154 : default so24,dil24,dil24b {
	newattr "$comment" = "4 of 16 Line Decoder/Demultiplexer" ;
	pin (a,b,c,d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,
	     y14,y15) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat ( a, b, c, d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,
	      y13,y14,y15)
	  to (23,22,21,20, 18, 19, 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 13, 14,
	       15, 16, 17) ;
	swap internal ( ((18,19)) ) ;
	}

part 74hct155 : default so16,dil16 {
	newattr "$comment" = "Dual 1 of 4 Decoder/Demultiplexer" ;
	pin (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3)
	  to (13, 3,  2, 1,  7,  6,  5,  4, 14, 15,  9, 10, 11, 12) ;
	}

part 74hct157 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74hct158 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74hct160 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Direct Clear" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74hct161 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Direct Clear" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74hct162 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Sync. Clear" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74hct163 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Sync. Clear" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74hct164 : default so14,dil14 {
	newattr "$comment" = "8 Bit Shift Register SIPO" ;
	pin (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh)
	  to (   9,  8,1,2, 3, 4, 5, 6,10,11,12,13) ;
	swap internal ( (( 1, 2)) ) ;
	}

part 74hct165 : default so16,dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	pin (shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh,/qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (shld,clkinh,clk,ser, a, b, c, d,e,f,g,h,qh,/qh)
	  to (   1,    15,  2, 10,11,12,13,14,3,4,5,6, 9,  7) ;
	}

part 74hct166 : default so16,dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	pin (/clr,shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clkinh,clk,ser,a,b,c,d, e, f, g, h,qh)
	  to (   9,  15,     6,  7,  1,2,3,4,5,10,11,12,14,13) ;
	}

part 74hct167 : default so16,dil16 {
	newattr "$comment" = "4 Bit Sync. Decade Rate Multiplier" ;
	pin (clk,stb,ei,uc,set9,clr,a,b,c,d,eo,y,z) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,stb,ei,uc,set9,clr, a, b,c,d,eo,y,z)
	  to (  9, 10,11,12,   4, 13,14,15,2,3, 7,6,5) ;
	}

part 74hct169 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Up/Down Counter" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74hct173 : default so16,dil16 {
	newattr "$comment" = "Quad D Register" ;
	pin (clr,m,n,/g1,/g2,clk,1d,1q,2d,2q,3d,3q,4d,4q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,m,n,/g1,/g2,clk,1d,1q,2d,2q,3d,3q,4d,4q)
	  to ( 15,1,2,  9, 10,  7,14, 3,13, 4,12, 5,11, 6) ;
	swap internal ( (( 1, 2)) ) ;
	swap internal ( (( 9,10)) ) ;
	}

part 74hct174 : default so16,dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	pin (/clr,clk,d1,q1,d2,q2,d3,d4,q3,q4,d5,q5,d6,q6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,d2,q2,d3,q3,d4,q4,d5,q5,d6,q6)
	  to (   1,  9, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  1, 9,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 74hct175 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (   1,  9, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  1, 9,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 74hct181 : default so24,dil24,dil24b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to ( 6, 5, 4, 3,8, 7,15,17,   14,    16,  2,  1,  9, 23, 22, 10,
	       21, 20, 11, 19, 18, 13) ;
	}

part 74hct182 : default so16,dil16 {
	newattr "$comment" = "16 Bit Look-Ahead Carry Generator" ;
	pin (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	     /g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	      /g)
	  to ( 13,  4,  3,  2,  1, 15, 14,  6,  5,    12,    11,     9, 7,
	      10) ;
	}

part 74hct189 : default so16,dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM inverting" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3)
	  to ( 1,15,14,13,  2, 3, 4,  5, 6,  7,10,  9,12, 11) ;
	}

part 74hct190 : default so16,dil16 {
	newattr "$comment" = "Synchronous Up/Down BCD Counter" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74hct191 : default so16,dil16 {
	newattr "$comment" = "Synchronous Up/Down Binary Counter" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74hct192 : default so16,dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock BCD Counter" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74hct193 : default so16,dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock Binary Counter" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74hct194 : default so16,dil16 {
	newattr "$comment" = "4 Bit Universal Shift Register PIPO" ;
	pin (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd)
	  to (   1, 9,10, 11,    2,3,15,4,14,5,13,6,    7,12) ;
	}

part 74hct195 : default so16,dil16 {
	newattr "$comment" = "4 Bit Shift Register PIPO" ;
	pin (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd)
	  to (   1,   9, 10,2, 3,4,15,5,14,6,13,7,12, 11) ;
	}

part 74hct219 : default so16,dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM inverting" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,15,14,13,  2, 3, 4, 5, 6, 7,10, 9,12,11) ;
	}

part 74hct221 : default so16,dil16 {
	newattr "$comment" = "Dual Monostable Multivibr., Schm.Trigger" ;
	pin (a,b,/clr,cx,"rx/cx",q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,"rx/cx", q,/q)
	  to (1, 2,   3,14,     15,13, 4)
	  or (9,10,  11, 6,      7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 74hct237 : default so16,dil16 {
	newattr "$comment" = "3 to 8 Bit Decoder/Demultiplexer" ;
	pin (/le,a0,a1,a2,e1,/e2,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/le,a0,a1,a2,e1,/e2,q0,q1,q2,q3,q4,q5,q6,q7)
	  to (  4, 1, 2, 3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 74hct238 : default so16,dil16 {
	newattr "$comment" = "3 to 8 Bit Decoder/Demultiplexer" ;
	pin (a0,a1,a2,/e1,/e2,e3,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,/e1,/e2,e3,q0,q1,q2,q3,q4,q5,q6,q7)
	  to ( 1, 2, 3,  4,  5, 6,15,14,13,12,11,10, 9, 7) ;
	swap internal ( (( 4, 5)) ) ;
	}

part 74hct239 : default dil16,so16 {
	newattr "$comment" = "Dual 2 to 4 Bit Decoder/Demultiplexer" ;
	pin (a0,a1,/e,q0,q1,q2,q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,/e,q0,q1,q2,q3)
	  to ( 2, 3, 1, 4, 5, 6, 7)
	  or (14,13,15,12,11,10, 9) ;
	swap ( ( 2, 3, 1, 4, 5, 6, 7), (14,13,15,12,11,10, 9) ) ;
	}

part 74hct240 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74hct241 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74hct242 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver inverting" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74hct243 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver noninverting" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74hct244 : default so20,dil20 {
	newattr "$comment" = "Octal Driver noninverting" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74hct245 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74hct251 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74hct253 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Multiplexer" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74hct257 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74hct258 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74hct259 : default so16,dil16 {
	newattr "$comment" = "8 Bit Addressable Set-Reset Latch" ;
	pin (s0,s1,s2,/g,d,/clr,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (s0,s1,s2,/g, d,/clr,q0,q1,q2,q3,q4,q5,q6,q7)
	  to ( 1, 2, 3,14,13,  15, 4, 5, 6, 7, 9,10,11,12) ;
	}

part 74hct273 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop" ;
	pin (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (   1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74hct280 : default so14,dil14 {
	newattr "$comment" = "9 Bit Odd/Even Parity Generator/Checker" ;
	pin (a,b,c,d,e,f,g,h,i,even,odd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,even,odd)
	  to (8,9,10,11,12,13,1,2,4,   5,  6) ;
	swap ( (( 8, 9,10,11,12,13, 1, 2, 4), 5, 6) ) ;
	}

part 74hct283 : default so16,dil16 {
	newattr "$comment" = "4 Bit Full Adder, Fast Carry" ;
	pin (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4)
	  to ( 5, 3,14,12, 6, 2,15,11, 7, 4, 1,13,10, 9) ;
	swap internal ( (( 5, 6),( 3, 2),(14,15),(12,11)) ) ;
	}

part 74hct297 : default so16,dil16 {
	newattr "$comment" = "Digital Phase Locked Loop" ;
	pin (a,b,c,d,kclk,du,enctr,idclk,pa1,pb,pa2,idout,xorpd,ecpd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b, c, d,kclk,du,enctr,idclk,pa1,pb,pa2,idout,xorpd,ecpd)
	  to (2,1,15,14,   4, 6,    3,    5,  9,10, 13,    7,   11,  12) ;
	}

part 74hct298 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer, Storage" ;
	pin (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd)
	  to (10, 11, 3, 2,15, 4, 1,14, 9, 5,13, 7, 6,12) ;
	swap ( [ 10,11,
	       ( 3, 2,15),
	       ( 4, 1,14),
	       ( 9, 5,13),
	       ( 7, 6,12) ] ) ;
	}

part 74hct299 : default so20,dil20 {
	newattr "$comment" = "8 Bit Universal PIPO Shift Register" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74hct323 : default so20,dil20 {
	newattr "$comment" = "8 Bit Shift/Storage Register" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74hct354 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74hct356 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74hct365 : default so16,dil16 {
	newattr "$comment" = "Hex Buffer W/Common Enable" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	swap internal ( (( 1,15)) ) ;
	}

part 74hct366 : default so16,dil16 {
	newattr "$comment" = "Hex Inverter W/Common Enable" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	swap internal ( (( 1,15)) ) ;
	}

part 74hct367 : default so16,dil16 {
	newattr "$comment" = "Hex Buffer 4 Bit and 2 Bit" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2,  3,  4,  5,  6,  7, 10,  9) ;
	xlat (/2g,2a1,2y1,2a2,2y2)
	  to ( 15, 12, 11, 14, 13) ;
	swap internal ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), (10, 9) ] ) ;
	swap internal ( [ 15, (12,11), (14,13) ] ) ;
	}

part 74hct368 : default so16,dil16 {
	newattr "$comment" = "Hex Inverter 4 Bit and 2 Bit" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2,  3,  4,  5,  6,  7, 10,  9) ;
	xlat (/2g,2a1,2y1,2a2,2y2)
	  to ( 15, 12, 11, 14, 13) ;
	swap internal ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), (10, 9) ] ) ;
	swap internal ( [ 15, (12,11), (14,13) ] ) ;
	}

part 74hct373 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74hct374 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74hct375 : default so16,dil16 {
	newattr "$comment" = "Quad Bistable Latch" ;
	pin (1d,c,1q,/1q,2d,2q,/2q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( c,1d,1q,/1q,2d,2q,/2q)
	  to ( 4, 1, 3,  2, 7, 5,  6)
	  or (12, 9,11, 10,15,13, 14) ;
	swap ( [  4, ( 1, 3, 2), ( 7, 5, 6) ],
	       [ 12, ( 9,11,10), (15,13,14) ] ) ;
	}

part 74hct377 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop with Data Enable" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to ( 11, 1, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [ 11, 1,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74hct384 : default so16,dil16 {
	newattr "$comment" = "8 by 1 Bit Two's-Complement Multiplier" ;
	pin (/clr,mode,clk,x0,x1,x2,x3,x4,x5,x6,x7,y,k,prod) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,mode,clk,x0,x1,x2,x3,x4,x5,x6,x7, y, k,prod)
	  to (   1,   9,  7, 5, 4, 3, 2,14,13,12,11,15,10,   6) ;
	}

part 74hct390 : default so16,dil16 {
	newattr "$comment" = "Dual 4 Bit Decade and Binary Counter" ;
	pin (/clr,a,qa,b,qb,qc,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr, a,qa, b,qb,qc,qd)
	  to (   2, 1, 3, 4, 5, 6, 7)
	  or (  14,15,13,12,11,10, 9) ;
	swap ( [  2, 1, 3, 4, 5, 6, 7 ],
	       [ 14,15,13,12,11,10, 9 ] ) ;
	}

part 74hct393 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Bit Decade and Binary Counter" ;
	pin (clr,a,qa,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (clr, a,qa,qb,qc,qd)
	  to (  2, 1, 3, 4, 5, 6)
	  or ( 12,13,11,10, 9, 8) ;
	swap ( ( 2, 1, 3, 4, 5, 6), (12,13,11,10, 9, 8) ) ;
	}

part 74hct423 : default so16,dil16 {
	newattr "$comment" = "Multivibrator (no Trigger from Clear)" ;
	pin (a,b,/clr,cx,rx,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,rx, q,/q)
	  to (1, 2,   3,14,15,13, 4)
	  or (9,10,  11, 6, 7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 74hct521 : default dil20,so20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74hct533 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Latch inverting" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74hct534 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74hct540 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74hct541 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74hct543 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register Transceiver" ;
	pin (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	     b4,a5,b5,a6,b6,a7,b7) ;
	net "vss" : (18) ;
	net "vcc" : (6) ;
	xlat (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	      b4,a5,b5,a6,b6,a7,b7)
	  to (  17,   16,   21,  19,   20,   15,22,14,23,13,24,12, 1,11, 2,
	      10, 3, 9, 4, 8, 5, 7) ;
	}

part 74hct544 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register Transceiver inverting" ;
	pin (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	     b4,a5,b5,a6,b6,a7,b7) ;
	net "vss" : (18) ;
	net "vcc" : (6) ;
	xlat (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	      b4,a5,b5,a6,b6,a7,b7)
	  to (  17,   16,   21,  19,   20,   15,22,14,23,13,24,12, 1,11, 2,
	      10, 3, 9, 4, 8, 5, 7) ;
	}

part 74hct545 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Line Driver inverting" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74hct563 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch inverting" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74hct564 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74hct573 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 2,19, 3,18, 4,17, 5,16, 6,15, 7,14, 8,13, 9,12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74hct574 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop (Data Flow Thru 374)" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 2,19, 3,18, 4,17, 5,16, 6,15, 7,14, 8,13, 9,12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74hct590 : default so16,dil16 {
	newattr "$comment" = "8 Bit Binary Counter, Output Register" ;
	pin (/g,rck,/ccken,cck,/cclr,/rco,qa,qb,qc,qd,qe,qf,qg,qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,rck,/ccken,cck,/cclr,/rco,qa,qb,qc,qd,qe,qf,qg,qh)
	  to (14, 13,    12, 11,   10,   9,15, 1, 2, 3, 4, 5, 6, 7) ;
	}

part 74hct592 : default so16,dil16 {
	newattr "$comment" = "8 Bit Binary Counter, Input Register" ;
	pin (/cclr,/ccken,cck,/cload,rck,/rco,a,b,c,d,e,f,g,h) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cclr,/ccken,cck,/cload,rck,/rco, a,b,c,d,e,f,g,h)
	  to (   10,    12, 11,    14, 13,   9,15,1,2,3,4,5,6,7) ;
	}

part 74hct595 : default dil16,so16 {
	newattr "$comment" = "8 Bit Shift Register, Output Register" ;
	pin (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'")
	  to (13, 12,   10, 11, 14,15, 1, 2, 3, 4, 5, 6, 7,    9) ;
	}

part 74hct597 : default so16,dil16 {
	newattr "$comment" = "8 Bit Shift Register, Input Register" ;
	pin (/sclr,sck,/sload,rck,ser,a,b,c,d,e,f,g,h,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/sclr,sck,/sload,rck,ser, a,b,c,d,e,f,g,h,"qh'")
	  to (   10, 11,    13, 12, 14,15,1,2,3,4,5,6,7,    9) ;
	}

part 74hct620 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74hct623 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74hct640 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74hct643 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver true inverting" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74hct645 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74hct646 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74hct648 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74hct651 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74hct652 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74hct670 : default so16,dil16 {
	newattr "$comment" = "4 by 4 Register File" ;
	pin (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to ( 5, 4,14,13, 12, 11,15,10, 1, 9, 2, 7, 3, 6) ;
	}

part 74hct688 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator, Output Enable" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74hct4002 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NOR Gate" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d, y)
	  to (2, 3, 4, 5, 1)
	  or (9,10,11,12,13) ;
	swap ( (( 2, 3, 4, 5), 1), (( 9,10,11,12),13) ) ;
	}

part 74hct4049 : default so16,dil16 {
	newattr "$comment" = "Hex Buffer/TTL Driver inverting" ;
	pin (a,y) ;
	net "vss" : (8) ;
	net "vcc" : (1) ;
	xlat ( a, y)
	  to ( 3, 2)
	  or ( 5, 4)
	  or ( 7, 6)
	  or ( 9,10)
	  or (11,12)
	  or (14,15) ;
	swap ( ( 3, 2), ( 5, 4), ( 7, 6), ( 9,10), (11,12), (14,15) ) ;
	}

part 74hct4050 : default so16,dil16 {
	newattr "$comment" = "Hex Buffer/TTL Driver noninverting" ;
	pin (a,y) ;
	net "vss" : (8) ;
	net "vcc" : (1) ;
	xlat ( a, y)
	  to ( 3, 2)
	  or ( 5, 4)
	  or ( 7, 6)
	  or ( 9,10)
	  or (11,12)
	  or (14,15) ;
	swap ( ( 3, 2), ( 5, 4), ( 7, 6), ( 9,10), (11,12), (14,15) ) ;
	}

part 74hct4075 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input OR Gate" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, c, y)
	  to ( 1, 2, 8, 9)
	  or ( 3, 4, 5, 6)
	  or (11,12,13,10) ;
	swap ( (( 1, 2, 8), 9), (( 3, 4, 5), 6), ((11,12,13),10) ) ;
	}

part 74hct4538 : default so16,dil16 {
	newattr "$comment" = "Dual Monostable Vibrators, Clear" ;
	pin ("+","-",/clr,cx,"rx/cx",q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ("+","-",/clr,cx,"rx/cx", q,/q)
	  to (  4,  5,   3, 1,      2, 6, 7)
	  or ( 12, 11,  13,15,     14,10, 9) ;
	swap ( ( 4, 5, 3, 1, 2, 6, 7), (12,11,13,15,14,10, 9) ) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.