loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d74f.def                                  */
/* SCM Library   : d74f.ddb                                  */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - Bipolar TTL FAST / Series 74F                           */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 74  = Commercial (0..70 Degree Celcius)   */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 74f00 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f02 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74f04 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74f06 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter/Buffer, 30V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74f07 : default so14,dil14 {
	newattr "$comment" = "Hex Buffer, 30V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74f08 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f09 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f10 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74f11 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74f13 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74f14 : default so14,dil14 {
	newattr "$comment" = "Hex Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74f20 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74f21 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74f27 : default so14,dil14 {
	newattr "$comment" = "Triple 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74f30 : default so14,dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 74f32 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f36 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Positive Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f37 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f38 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f40 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74f51 : mainpart so14,dil14 {
	newattr "$comment" = "3-3/2-2 Input AND-OR-Invert Gates" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c,d, e, f,y)
	  to (1,12,13,9,10,11,8) ;
	swap ( [  (( 1,12,13)), (( 9,10,11)), 8 ] ) ;
	}

part 74f51x : subpart 74f51 {
	pin (a,b,c,d,y) ;
	xlat (a,b,c,d,y)
	  to (2,3,4,5,6) ;
	swap ( [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 74f64 : default so14,dil14 {
	newattr "$comment" = "4-2-3-2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,k,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d, e,f,g,h,i,j,k,y)
	  to (9,10,11,12,13,1,2,3,4,5,6,8) ;
	swap internal ( (( 9,10)), (( 2, 3)) ) ;
	swap internal ( ((11,12,13, 1)) ) ;
	swap internal ( (( 4, 5, 6)) ) ;
	}

part 74f74 : default so14,dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 74f83 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Full Adder, Fast Carry" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,ci,y0,y1,y2,y3,co) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,ci,y0,y1,y2,y3,co)
	  to (10, 8, 3, 1,11, 7, 4,16,13, 9, 6, 2,15,14) ;
	swap internal ( (10, 8, 3, 1), (11, 7, 4,16) ) ;
	}

part 74f85 : default so16,dil16 {
	newattr "$comment" = "4 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q")
	  to (10,12,13,15, 9,11,14, 1,    2,    3,    4,    7,    6,    5) ;
	swap internal ( (10,12,13,15, 2, 7), ( 9,11,14, 1, 4, 5) ) ;
	}

part 74f86 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f109 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,/k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk,/k,/clr, q,/q)
	  to (   5, 2,  4, 3,   1, 6, 7)
	  or (  11,14, 12,13,  15,10, 9) ;
	swap ( ( 5, 2, 4, 3, 1, 6, 7), (11,14,12,13,15,10, 9) ) ;
	}

part 74f112 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   4, 3,  1, 2,  15,5, 6)
	  or (  10,11, 13,12,  14,9, 7) ;
	swap ( ( 4, 3, 1, 2,15, 5, 6), (10,11,13,12,14, 9, 7) ) ;
	}

part 74f113 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre, j,clk, k,q,/q)
	  to (   4, 3,  1, 2,5, 6)
	  or (  10,11, 13,12,9, 8) ;
	swap ( ( 4, 3, 1, 2, 5, 6), (10,11,13,12, 9, 8) ) ;
	}

part 74f114 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (   1, 13,    4, 3, 2, 5,  6,   10,11,12, 9,  8) ;
	swap ( [  1,13, ( 4, 3, 2, 5, 6), (10,11,12, 9, 8) ] ) ;
	}

part 74f125 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 74f126 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 74f132 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74f133 : default so16,dil16 {
	newattr "$comment" = "13 Input Positive NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,k,l,m,y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,d,e,f,g, h, i, j, k, l, m,y)
	  to (1,2,3,4,5,6,7,10,11,12,13,14,15,9) ;
	swap ( (( 1, 2, 3, 4, 5, 6, 7,10,11,12,13,14,15), 9) ) ;
	}

part 74f138 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (1,2,3, 6,   4,   5,15,14,13,12,11,10, 9, 7) ;
	swap internal ( (( 4, 5)) ) ;
	}

part 74f139 : default so16,dil16 {
	newattr "$comment" = "Dual 2 of 4 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,/g,y0,y1,y2,y3)
	  to ( 2, 3, 1, 4, 5, 6, 7)
	  or (14,13,15,12,11,10, 9) ;
	swap ( ( 2, 3, 1, 4, 5, 6, 7), (14,13,15,12,11,10, 9) ) ;
	}

part 74f148 : default so16,dil16 {
	newattr "$comment" = "8 to 3 Octal Priority Encoder" ;
	newattr "$ttlout" = "TP" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2)
	  to (10,11,12,13, 1, 2, 3, 4, 5,15,14, 9, 7, 6) ;
	}

part 74f151 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74f153 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74f154 : default dil24,dil24b {
	newattr "$comment" = "4 of 16 Line Decoder/Demultiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,
	     y14,y15) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat ( a, b, c, d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,
	      y13,y14,y15)
	  to (23,22,21,20, 18, 19, 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 13, 14,
	       15, 16, 17) ;
	swap internal ( ((18,19)) ) ;
	}

part 74f157 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74f158 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74f160 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74f161 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74f162 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74f163 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74f164 : default so14,dil14 {
	newattr "$comment" = "8 Bit Shift Register SIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh)
	  to (   9,  8,1,2, 3, 4, 5, 6,10,11,12,13) ;
	swap internal ( (( 1, 2)) ) ;
	}

part 74f166 : default so16,dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clkinh,clk,ser,a,b,c,d, e, f, g, h,qh)
	  to (   9,  15,     6,  7,  1,2,3,4,5,10,11,12,14,13) ;
	}

part 74f168 : default dil16 {
	newattr "$comment" = "4 Bit Decade Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74f169 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74f174 : default so16,dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,d2,q2,d3,d4,q3,q4,d5,q5,d6,q6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,d2,q2,d3,q3,d4,q4,d5,q5,d6,q6)
	  to (   1,  9, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  1, 9,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 74f175 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (   1,  9, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  1, 9,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 74f181 : default so24,dil24,dil24b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to ( 6, 5, 4, 3,8, 7,15,17,   14,    16,  2,  1,  9, 23, 22, 10,
	       21, 20, 11, 19, 18, 13) ;
	}

part 74f182 : default so16,dil16 {
	newattr "$comment" = "16 Bit Look-Ahead Carry Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	     /g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	      /g)
	  to ( 13,  4,  3,  2,  1, 15, 14,  6,  5,    12,    11,     9, 7,
	      10) ;
	}

part 74f189 : default so16,dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3)
	  to ( 1,15,14,13,  2, 3, 4,  5, 6,  7,10,  9,12, 11) ;
	}

part 74f190 : default so16,dil16 {
	newattr "$comment" = "Synchronous Up/Down BCD Counter" ;
	newattr "$ttlout" = "OC" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74f191 : default so16,dil16 {
	newattr "$comment" = "Synchronous Up/Down Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74f192 : default so16,dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock BCD Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74f193 : default so16,dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74f194 : default so16,dil16 {
	newattr "$comment" = "4 Bit Universal Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd)
	  to (   1, 9,10, 11,    2,3,15,4,14,5,13,6,    7,12) ;
	}

part 74f195 : default so16,dil16 {
	newattr "$comment" = "4 Bit Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd)
	  to (   1,   9, 10,2, 3,4,15,5,14,6,13,7,12, 11) ;
	}

part 74f198 : default dil24,dil24b {
	newattr "$comment" = "8 Bit Universal Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,h,slser,
	     qh) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,qd, e,qe, f,qf, g,qg,
	       h,slser,qh)
	  to (  13, 1,23, 11,    2,3, 4,5, 6,7, 8,9,10,15,14,17,16,19,18,
	      21,   22,20) ;
	}

part 74f240 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f241 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f242 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74f243 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74f244 : default so20,dil20 {
	newattr "$comment" = "Octal Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f245 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f251 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74f253 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74f257 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74f258 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74f259 : default so16,dil16 {
	newattr "$comment" = "8 Bit Addressable Set-Reset Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,/g,d,/clr,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (s0,s1,s2,/g, d,/clr,q0,q1,q2,q3,q4,q5,q6,q7)
	  to ( 1, 2, 3,14,13,  15, 4, 5, 6, 7, 9,10,11,12) ;
	}

part 74f260 : default so14,dil14 {
	newattr "$comment" = "Dual 5 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c, d, e,y)
	  to (1,2,3,12,13,5)
	  or (4,8,9,10,11,6) ;
	swap ( (( 1, 2, 3,12,13), 5), (( 4, 8, 9,10,11), 6) ) ;
	}

part 74f273 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (   1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74f280 : default so14,dil14 {
	newattr "$comment" = "9 Bit Odd/Even Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,even,odd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,even,odd)
	  to (8,9,10,11,12,13,1,2,4,   5,  6) ;
	swap ( (( 8, 9,10,11,12,13, 1, 2, 4), 5, 6) ) ;
	}

part 74f283 : default so16,dil16 {
	newattr "$comment" = "4 Bit Full Adder, Fast Carry" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4)
	  to ( 5, 3,14,12, 6, 2,15,11, 7, 4, 1,13,10, 9) ;
	swap internal ( (( 5, 6),( 3, 2),(14,15),(12,11)) ) ;
	}

part 74f286 : default so14,dil14 {
	newattr "$comment" = "9 Bit Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,/xmit,pario,parerr) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,/xmit,pario,parerr)
	  to (8,9,10,11,12,13,1,2,4,    3,    6,     5) ;
	swap internal ( (( 8, 9,10,11,12,13, 1, 2, 4)) ) ;
	}

part 74f298 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer, Storage" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd)
	  to (10, 11, 3, 2,15, 4, 1,14, 9, 5,13, 7, 6,12) ;
	swap ( [ 10,11,
	       ( 3, 2,15),
	       ( 4, 1,14),
	       ( 9, 5,13),
	       ( 7, 6,12) ] ) ;
	}

part 74f299 : default so20,dil20 {
	newattr "$comment" = "8 Bit Universal PIPO Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74f322 : default so20,dil20 {
	newattr "$comment" = "8 Bit Shift Register, Sign Extend" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/oe,/g,"s/p",clk,/se,ds,d0,d1,"a/qa","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh","qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/oe,/g,"s/p",clk,/se,ds,d0,d1,"a/qa","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh","qh'")
	  to (   9,  8, 1,    2, 11, 18,19, 3,17,     4,    16,     5,    15,
	           6,    14,     7,    13,   12) ;
	}

part 74f323 : default so20,dil20 {
	newattr "$comment" = "8 Bit Shift/Storage Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74f352 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74f353 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74f365 : default so16,dil16 {
	newattr "$comment" = "Hex Buffer W/Common Enable" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	swap internal ( (( 1,15)) ) ;
	}

part 74f366 : default so16,dil16 {
	newattr "$comment" = "Hex Inverter W/Common Enable" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	swap internal ( (( 1,15)) ) ;
	}

part 74f367 : default so16,dil16 {
	newattr "$comment" = "Hex Buffer 4 Bit and 2 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2,  3,  4,  5,  6,  7, 10,  9) ;
	xlat (/2g,2a1,2y1,2a2,2y2)
	  to ( 15, 12, 11, 14, 13) ;
	swap internal ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), (10, 9) ] ) ;
	swap internal ( [ 15, (12,11), (14,13) ] ) ;
	}

part 74f368 : default so16,dil16 {
	newattr "$comment" = "Hex Inverter 4 Bit and 2 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2,  3,  4,  5,  6,  7, 10,  9) ;
	xlat (/2g,2a1,2y1,2a2,2y2)
	  to ( 15, 12, 11, 14, 13) ;
	swap internal ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), (10, 9) ] ) ;
	swap internal ( [ 15, (12,11), (14,13) ] ) ;
	}

part 74f373 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74f374 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74f377 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop with Data Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to ( 11, 1, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [ 11, 1,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74f378 : default so16,dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q)
	  to (  9, 1, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  9, 1,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 74f379 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,/1q,2d,2q,/2q,3d,3q,/3q,4d,4q,/4q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,/g,1d,1q,/1q,2d,2q,/2q,3d,3q,/3q,4d,4q,/4q)
	  to (  9, 1, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  9, 1,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 74f381 : default so20,dil20 {
	newattr "$comment" = "ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,cn,/p,/g,a0,b0,f0,a1,b1,f1,a2,b2,f2,a3,b3,f3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,s2,cn,/p,/g,a0,b0,f0,a1,b1,f1,a2,b2,f2,a3,b3,f3)
	  to ( 5, 6, 7,15,14,13, 3, 4, 8, 1, 2, 9,19,18,11,17,16,12) ;
	}

part 74f382 : default so20,dil20 {
	newattr "$comment" = "4 Bit Arithemetic Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,cn,a0,b0,f0,a1,b1,f1,a2,b2,a3,b3,f2,ovr,"cn+4",f3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,s2,cn,a0,b0,f0,a1,b1,f1,a2,b2,a3,b3,f2,ovr,"cn+4",f3)
	  to ( 5, 6, 7,15, 3, 4, 8, 1, 2, 9,19,18,17,16,11, 13,    14,12) ;
	}

part 74f385 : default so20,dil20 {
	newattr "$comment" = "Quad Serial Adder/Substractor" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,"1s/a",1a,1b,1s,"2s/a",2a,2b,2s,"3s/a",3a,3b,3s,"4s/a",
	     4a,4b,4s) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,clk,"1s/a",1a,1b,1s,"2s/a",2a,2b,2s,"3s/a",3a,3b,3s,"4s/a",
	      4a,4b,4s)
	  to (  11,  1,     3, 5, 4, 2,     8, 6, 7, 9,    13,15,14,12,    18,
	      16,17,19) ;
	swap ( [ 11, 1,
	       ( 3, 5, 4, 2),
	       ( 8, 6, 7, 9),
	       (13,15,14,12),
	       (18,16,17,19) ] ) ;
	}

part 74f393 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Bit Decade and Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,a,qa,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (clr, a,qa,qb,qc,qd)
	  to (  2, 1, 3, 4, 5, 6)
	  or ( 12,13,11,10, 9, 8) ;
	swap ( ( 2, 1, 3, 4, 5, 6), (12,13,11,10, 9, 8) ) ;
	}

part 74f395 : default so16,dil16 {
	newattr "$comment" = "4 Bit Cascadable Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd,"qd'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd,"qd'")
	  to (   1,  9,   7, 10,  2,3,15,4,14,5,13,6,12,   11) ;
	}

part 74f398 : default so20,dil20 {
	newattr "$comment" = "Quad 2 Input Multiplexer, Storage" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,ck,a1,a2,qa,/qa,b1,b2,qb,/qb,c1,c2,qc,/qc,d1,d2,qd,/qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (ws,ck,a1,a2,qa,/qa,b1,b2,qb,/qb,c1,c2,qc,/qc,d1,d2,qd,/qd)
	  to ( 1,11, 4, 5, 2,  3, 7, 6, 9,  8,14,15,12, 13,17,16,19, 18) ;
	swap ( [  1,11,
	       ( 4, 5, 2, 3),
	       ( 7, 6, 9, 8),
	       (14,15,12,13),
	       (17,16,19,18) ] ) ;
	}

part 74f399 : default so16,dil16 {
	newattr "$comment" = "Quad 2 Input MUX, Storage (25LS09)" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,ck,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ws,ck,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd)
	  to ( 1, 9, 3, 4, 2, 6, 5, 7,11,12,10,14,13,15) ;
	swap ( [  1, 9,
	       ( 3, 4, 2),
	       ( 6, 5, 7),
	       (11,12,10),
	       (14,13,15) ] ) ;
	}

part 74f518 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,   19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74f519 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,   19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74f520 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74f521 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74f522 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74f533 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74f534 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74f538 : default so20,dil20 {
	newattr "$comment" = "3 of 8 Decoder" ;
	newattr "$ttlout" = "TS" ;
	pin (al,/oe1,/oe2,a,b,c,g1,g2,/g3,/g4,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (al,/oe1,/oe2,a,b, c,g1,g2,/g3,/g4,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (12,   4,   5,6,7,17,13,14, 15, 16, 3, 2, 1,19,18, 8, 9,11) ;
	swap internal ( (( 4, 5)) ) ;
	swap internal ( ((13,14)) ) ;
	swap internal ( ((15,16)) ) ;
	}

part 74f539 : default so20,dil20 {
	newattr "$comment" = "Dual 1 of 4 Decoder" ;
	newattr "$ttlout" = "TS" ;
	pin (al,/oe,a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (al,/oe, a, b,/g,y0,y1,y2,y3)
	  to ( 4,  5,17,18,16, 3, 2, 1,19)
	  or (13, 14, 6, 7,15,12,11, 9, 8) ;
	swap ( ( 4, 5,17,18,16, 3, 2, 1,19),
	       (13,14, 6, 7,15,12,11, 9, 8) ) ;
	}

part 74f540 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74f541 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74f543 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	     b4,a5,b5,a6,b6,a7,b7) ;
	net "vss" : (18) ;
	net "vcc" : (6) ;
	xlat (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	      b4,a5,b5,a6,b6,a7,b7)
	  to (  17,   16,   21,  19,   20,   15,22,14,23,13,24,12, 1,11, 2,
	      10, 3, 9, 4, 8, 5, 7) ;
	}

part 74f544 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	     b4,a5,b5,a6,b6,a7,b7) ;
	net "vss" : (18) ;
	net "vcc" : (6) ;
	xlat (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	      b4,a5,b5,a6,b6,a7,b7)
	  to (  17,   16,   21,  19,   20,   15,22,14,23,13,24,12, 1,11, 2,
	      10, 3, 9, 4, 8, 5, 7) ;
	}

part 74f545 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f563 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74f564 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74f568 : default so20,dil20 {
	newattr "$comment" = "4 Bit Decade Counter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (17,    1,  2,  12,   7,    9,   11,    8,  18,  19,3,16,4,15,
	      5,14,6,13) ;
	}

part 74f569 : default so20,dil20 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (17,    1,  2,  12,   7,    9,   11,    8,  18,  19,3,16,4,15,
	      5,14,6,13) ;
	}

part 74f573 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 2,19, 3,18, 4,17, 5,16, 6,15, 7,14, 8,13, 9,12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74f574 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop (Data Flow Thru 374)" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 2,19, 3,18, 4,17, 5,16, 6,15, 7,14, 8,13, 9,12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74f595 : default so16,dil16 {
	newattr "$comment" = "8 Bit Shift Register, Output Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'")
	  to (13, 12,   10, 11, 14,15, 1, 2, 3, 4, 5, 6, 7,    9) ;
	}

part 74f597 : default so16,dil16 {
	newattr "$comment" = "8 Bit Shift Register, Input Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/sclr,sck,/sload,rck,ser,a,b,c,d,e,f,g,h,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/sclr,sck,/sload,rck,ser, a,b,c,d,e,f,g,h,"qh'")
	  to (   10, 11,    13, 12, 14,15,1,2,3,4,5,6,7,    9) ;
	}

part 74f604 : default so28,dil28b {
	newattr "$comment" = "Octal 2 Input Multiplexed Register" ;
	newattr "$ttlout" = "TS" ;
	pin ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	     y6,a7,b7,y7,a8,b8,y8) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	      y6,a7,b7,y7,a8,b8,y8)
	  to (    2,  1, 3, 4,15, 5, 6,13, 7, 8,12, 9,10,11,27,26,16,25,24,
	      17,23,22,18,21,20,19) ;
	swap ( [  2, 1,
	       ( 3, 4,15),
	       ( 5, 6,13),
	       ( 7, 8,12),
	       ( 9,10,11),
	       (27,26,16),
	       (25,24,17),
	       (23,22,18),
	       (21,20,19) ] ) ;
	}

part 74f605 : default so28,dil28b {
	newattr "$comment" = "Octal 2 Input Multiplexed Register" ;
	newattr "$ttlout" = "OC" ;
	pin ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	     y6,a7,b7,y7,a8,b8,y8) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	      y6,a7,b7,y7,a8,b8,y8)
	  to (    2,  1, 3, 4,15, 5, 6,13, 7, 8,12, 9,10,11,27,26,16,25,24,
	      17,23,22,18,21,20,19) ;
	swap ( [  2, 1,
	       ( 3, 4,15),
	       ( 5, 6,13),
	       ( 7, 8,12),
	       ( 9,10,11),
	       (27,26,16),
	       (25,24,17),
	       (23,22,18),
	       (21,20,19) ] ) ;
	}

part 74f620 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f621 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f622 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f623 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f640 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f641 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f642 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f646 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74f647 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74f648 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74f649 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74f651 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74f652 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74f653 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74f654 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74f670 : default so16,dil16 {
	newattr "$comment" = "4 by 4 Register File" ;
	newattr "$ttlout" = "TS" ;
	pin (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to ( 5, 4,14,13, 12, 11,15,10, 1, 9, 2, 7, 3, 6) ;
	}

part 74f674 : default so24,dil24,dil24b {
	newattr "$comment" = "16 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (mode,"r/w",/cs,clk,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,
	     p13,p14,p15,ser) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (mode,"r/w",/cs,clk,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,
	      p13,p14,p15,ser)
	  to (   5,    3,  1,  2, 7, 8, 9,10,11,13,14,15,16,17, 18, 19, 20,
	       21, 22, 23,  6) ;
	}

part 74f756 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f757 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f760 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f804 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input NAND Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74f805 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input NOR Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74f821 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit D-FF/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	     10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,
	      9q,10d,10q)
	  to (  1, 13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,
	      15, 11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74f822 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit D-FF/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	     8q,/9d,9q,/10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	      8q,/9d,9q,/10d,10q)
	  to (  1, 13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,  8,17,  9,
	      16, 10,15,  11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74f823 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit D-FF/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,
	     8d,8q,9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,
	      7q,8d,8q,9d,9q)
	  to (  1,  11,    14, 13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,
	      17, 9,16,10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74f824 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit D-FF/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,
	     /7d,7q,/8d,8q,/9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,
	      6q,/7d,7q,/8d,8q,/9d,9q)
	  to (  1,  11,    14, 13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,
	      18,  8,17,  9,16, 10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74f825 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register noninv" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,
	     6d,6q,7d,7q,8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,
	      6d,6q,7d,7q,8d,8q)
	  to (   1,   2,  23,  11,    14, 13, 3,22, 4,21, 5,20, 6,19, 7,18,
	       8,17, 9,16,10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74f826 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,
	     5q,/6d,6q,/7d,7q,/8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,
	      /5d,5q,/6d,6q,/7d,7q,/8d,8q)
	  to (   1,   2,  23,  11,    14, 13,  3,22,  4,21,  5,20,  6,19,
	        7,18,  8,17,  9,16, 10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74f841 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	     10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	      10d,10q)
	  to (  1,13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,15,
	       11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74f842 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit Transparent Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,8q,
	     /9d,9q,/10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	      8q,/9d,9q,/10d,10q)
	  to (  1,13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,  8,17,  9,
	      16, 10,15,  11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74f843 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/pre,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,
	     8q,9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/pre, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,
	      8d,8q,9d,9q)
	  to (  1,  11,  14,13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17,
	       9,16,10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74f844 : default dil24,dil24b {
	newattr "$comment" = "9 Bit Transparent Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/pre,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,
	     7q,/8d,8q,/9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/pre, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,
	      /7d,7q,/8d,8q,/9d,9q)
	  to (  1,  14,  11,13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,
	        8,17,  9,16, 10,15) ;
	swap ( [  1,14,11,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74f845 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Latch noninv" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/pre,/clr,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,
	     6q,7d,7q,8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/pre,/clr, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,
	      6q,7d,7q,8d,8q)
	  to (   1,   2,  23,  14,  11,13, 3,22, 4,21, 5,20, 6,19, 7,18, 8,
	      17, 9,16,10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74f846 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/pre,/clr,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,
	     /6d,6q,/7d,7q,/8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/pre,/clr, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,
	      5q,/6d,6q,/7d,7q,/8d,8q)
	  to (   1,   2,  23,  14,  11,13,  3,22,  4,21,  5,20,  6,19,  7,
	      18,  8,17,  9,16, 10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74f881 : default so24,dil24,dil24b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to ( 6, 5, 4, 3,8, 7,15,17,   14,    16,  2,  1,  9, 23, 22, 10,
	       21, 20, 11, 19, 18, 13) ;
	}

part 74f882 : default so24,dil24,dil24b {
	newattr "$comment" = "32 Bit Look-Ahead Carry Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,/p4,/g4,/p5,/g5,/p6,/g6,/p7,
	     /g7,"cn+8","cn+16","cn+24","cn+32") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,/p4,/g4,/p5,/g5,/p6,/g6,
	      /p7,/g7,"cn+8","cn+16","cn+24","cn+32")
	  to ( 1,  3,  2,  5,  4,  8,  7, 10,  9, 14, 13, 16, 15, 19, 18,
	       21, 20,     6,     11,     17,     22) ;
	}

part 74f1240 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 240" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f1241 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 241" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f1242 : default so14,dil14 {
	newattr "$comment" = "Reduced Power 242" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74f1243 : default so14,dil14 {
	newattr "$comment" = "Reduced Power 243" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74f1244 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 244" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74f1245 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceivers" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74f1804 : default so20,dil20 {
	newattr "$comment" = "804 with Center Pinning" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (15) ;
	net "vcc" : (5) ;
	xlat ( a, b, y)
	  to ( 6, 7, 8)
	  or ( 9,10,11)
	  or (12,13,14)
	  or (17,18,16)
	  or (20, 1,19)
	  or ( 3, 4, 2) ;
	swap ( (( 6, 7), 8),
	       (( 9,10),11),
	       ((12,13),14),
	       ((17,18),16),
	       ((20, 1),19),
	       (( 3, 4), 2) ) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.