loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d74as.def                                 */
/* SCM Library   : d74as.ddb                                 */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - Bipolar TTL Advanced Schottky / Series 74AS             */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 74  = Commercial (0..70 Degree Celcius)   */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 74as00 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as02 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74as04 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74as08 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as10 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74as11 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74as20 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74as21 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74as27 : default so14,dil14 {
	newattr "$comment" = "Triple 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74as30 : default so14,dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 74as32 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as34 : default so14,dil14 {
	newattr "$comment" = "Hex Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74as74 : default so14,dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 74as86 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as95 : default so14,dil14 {
	newattr "$comment" = "4 Bit Shift Register PISO" ;
	newattr "$ttlout" = "TP" ;
	pin (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd)
	  to (   6,   9,   8,  1,2,13,3,12,4,11,5,10) ;
	}

part 74as109 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,/k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk,/k,/clr, q,/q)
	  to (   5, 2,  4, 3,   1, 6, 7)
	  or (  11,14, 12,13,  15,10, 9) ;
	swap ( ( 5, 2, 4, 3, 1, 6, 7), (11,14,12,13,15,10, 9) ) ;
	}

part 74as112 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   4, 3,  1, 2,  15,5, 6)
	  or (  10,11, 13,12,  14,9, 7) ;
	swap ( ( 4, 3, 1, 2,15, 5, 6), (10,11,13,12,14, 9, 7) ) ;
	}

part 74as113 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre, j,clk, k,q,/q)
	  to (   4, 3,  1, 2,5, 6)
	  or (  10,11, 13,12,9, 8) ;
	swap ( ( 4, 3, 1, 2, 5, 6), (10,11,13,12, 9, 8) ) ;
	}

part 74as114 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (   1, 13,    4, 3, 2, 5,  6,   10,11,12, 9,  8) ;
	swap ( [  1,13, ( 4, 3, 2, 5, 6), (10,11,12, 9, 8) ] ) ;
	}

part 74as131 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder, Address Registers" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (  4,1,2,3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 74as136 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as137 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder, Address Registers" ;
	newattr "$ttlout" = "TP" ;
	pin (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (  4,1,2,3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 74as138 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (1,2,3, 6,   4,   5,15,14,13,12,11,10, 9, 7) ;
	swap internal ( (( 4, 5)) ) ;
	}

part 74as139 : default so16,dil16 {
	newattr "$comment" = "Dual 2 of 4 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,/g,y0,y1,y2,y3)
	  to ( 2, 3, 1, 4, 5, 6, 7)
	  or (14,13,15,12,11,10, 9) ;
	swap ( ( 2, 3, 1, 4, 5, 6, 7), (14,13,15,12,11,10, 9) ) ;
	}

part 74as150 : default so24,dil24,dil24b {
	newattr "$comment" = "16 Bit Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,/g,e0,e1,e2,e3,e4,e5,e6,e7,e8,e9,e10,e11,e12,e13,e14,
	     e15,w) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat ( a, b, c, d,/g,e0,e1,e2,e3,e4,e5,e6,e7,e8,e9,e10,e11,e12,e13,
	      e14,e15, w)
	  to (15,14,13,11, 9, 8, 7, 6, 5, 4, 3, 2, 1,23,22, 21, 20, 19, 18,
	       17, 16,10) ;
	}

part 74as151 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74as153 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74as157 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74as158 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74as160 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74as161 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74as162 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74as163 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74as168 : default dil16 {
	newattr "$comment" = "4 Bit Decade Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74as169 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74as174 : default so16,dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,d2,q2,d3,d4,q3,q4,d5,q5,d6,q6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,d2,q2,d3,q3,d4,q4,d5,q5,d6,q6)
	  to (   1,  9, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  1, 9,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 74as175 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (   1,  9, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  1, 9,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 74as181 : default so24,dil24,dil24b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to ( 6, 5, 4, 3,8, 7,15,17,   14,    16,  2,  1,  9, 23, 22, 10,
	       21, 20, 11, 19, 18, 13) ;
	}

part 74as182 : default dil16 {
	newattr "$comment" = "16 Bit Look-Ahead Carry Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	     /g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	      /g)
	  to ( 13,  4,  3,  2,  1, 15, 14,  6,  5,    12,    11,     9, 7,
	      10) ;
	}

part 74as194 : default so16,dil16 {
	newattr "$comment" = "4 Bit Universal Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd)
	  to (   1, 9,10, 11,    2,3,15,4,14,5,13,6,    7,12) ;
	}

part 74as195 : default dil16 {
	newattr "$comment" = "4 Bit Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd)
	  to (   1,   9, 10,2, 3,4,15,5,14,6,13,7,12, 11) ;
	}

part 74as230 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2,2a3,
	     2y3,2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (/2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to ( 19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as231 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as240 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as241 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as242 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74as243 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74as244 : default so20,dil20 {
	newattr "$comment" = "Octal Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as245 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as250 : default so24,dil24,dil24b {
	newattr "$comment" = "16 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,a,b,c,d,e0,e1,e2,e3,e4,e5,e6,e7,e8,e9,e10,e11,e12,e13,e14,
	     e15,/w) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g, a, b, c, d,e0,e1,e2,e3,e4,e5,e6,e7,e8,e9,e10,e11,e12,e13,
	      e14,e15,/w)
	  to ( 9,15,14,13,11, 8, 7, 6, 5, 4, 3, 2, 1,23,22, 21, 20, 19, 18,
	       17, 16,10) ;
	}

part 74as251 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74as253 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74as257 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74as258 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74as264 : default dil16 {
	newattr "$comment" = "Counter Look-Ahead" ;
	newattr "$ttlout" = "TP" ;
	pin (ce,b0,a0,b1,a1,b2,a2,b3,a3,c0,c1,c2,rcoa,rcob) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ce,b0,a0,b1,a1,b2,a2,b3,a3,c0,c1,c2,rcoa,rcob)
	  to (13, 4, 3, 2, 1,15,14, 6, 5,12,11, 9,  10,   7) ;
	}

part 74as280 : default so14,dil14 {
	newattr "$comment" = "9 Bit Odd/Even Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,even,odd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,even,odd)
	  to (8,9,10,11,12,13,1,2,4,   5,  6) ;
	swap ( (( 8, 9,10,11,12,13, 1, 2, 4), 5, 6) ) ;
	}

part 74as282 : default dil20 {
	newattr "$comment" = "16 Bit Look-Ahead Carry Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,cna,cnb,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn'","cn+x","cn+y",
	     "cn+z",/p,/g) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,cna,cnb,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn'","cn+x",
	      "cn+y","cn+z",/p,/g)
	  to ( 7, 8, 17, 16,  4,  3,  2,  1, 19, 18,  6,  5,   13,    15,
	          14,    11, 9,12) ;
	}

part 74as286 : default so14,dil14 {
	newattr "$comment" = "9 Bit Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,/xmit,pario,parerr) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,/xmit,pario,parerr)
	  to (8,9,10,11,12,13,1,2,4,    3,    6,     5) ;
	swap internal ( (( 8, 9,10,11,12,13, 1, 2, 4)) ) ;
	}

part 74as298 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer, Storage" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd)
	  to (10, 11, 3, 2,15, 4, 1,14, 9, 5,13, 7, 6,12) ;
	swap ( [ 10,11,
	       ( 3, 2,15),
	       ( 4, 1,14),
	       ( 9, 5,13),
	       ( 7, 6,12) ] ) ;
	}

part 74as299 : default so20,dil20 {
	newattr "$comment" = "8 Bit Universal PIPO Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74as323 : default so20,dil20 {
	newattr "$comment" = "8 Bit Shift/Storage Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74as352 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74as353 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74as373 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74as374 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74as395 : default so16,dil16 {
	newattr "$comment" = "4 Bit Cascadable Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd,"qd'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd,"qd'")
	  to (   1,  9,   7, 10,  2,3,15,4,14,5,13,6,12,   11) ;
	}

part 74as533 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74as534 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74as573 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 2,19, 3,18, 4,17, 5,16, 6,15, 7,14, 8,13, 9,12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74as574 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop (Data Flow Thru 374)" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 2,19, 3,18, 4,17, 5,16, 6,15, 7,14, 8,13, 9,12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74as575 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal D-Flip-Flop (574 with Clear)" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  2, 14,   1, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,15) ;
	swap ( [  2,14, 1,
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74as576 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74as577 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal D-Flip-Flop (576 with Clear)" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,
	     8d,/8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,
	      8d,/8q)
	  to (  2, 14,   1, 3, 22, 4, 21, 5, 20, 6, 19, 7, 18, 8, 17, 9, 16,
	      10, 15) ;
	swap ( [  2,14, 1,
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74as580 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74as620 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as621 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as622 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as623 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as638 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as639 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as640 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as641 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as642 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as643 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver true inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as644 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as645 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as646 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74as648 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74as651 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74as652 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74as756 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as757 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as758 : default so14,dil14 {
	newattr "$comment" = "Quad Transceiver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74as759 : default so14,dil14 {
	newattr "$comment" = "Quad Transceiver noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74as760 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as762 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2,2a3,
	     2y3,2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (/2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to ( 19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as763 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Driver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74as800 : default so20,dil20 {
	newattr "$comment" = "Triple 4 Input AND/NAND Driver" ;
	pin (a,b,c,d,y,z) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (a, b, c, d, y, z)
	  to (1,17,18,19,16,15)
	  or (2, 3, 4, 5,14,13)
	  or (6, 7, 8, 9,12,11) ;
	swap ( (( 1,17,18,19),16,15),
	       (( 2, 3, 4, 5),14,13),
	       (( 6, 7, 8, 9),12,11) ) ;
	}

part 74as802 : default so20,dil20 {
	newattr "$comment" = "Triple 4 Input OR/NOR Driver" ;
	pin (a,b,c,d,y,z) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (a, b, c, d, y, z)
	  to (1,17,18,19,16,15)
	  or (2, 3, 4, 5,14,13)
	  or (6, 7, 8, 9,12,11) ;
	swap ( (( 1,17,18,19),16,15),
	       (( 2, 3, 4, 5),14,13),
	       (( 6, 7, 8, 9),12,11) ) ;
	}

part 74as804 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input NAND Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74as805 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input NOR Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74as808 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input AND Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74as810 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as811 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive NOR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as821 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit D-FF/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	     10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,
	      9q,10d,10q)
	  to (  1, 13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,
	      15, 11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74as822 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit D-FF/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	     8q,/9d,9q,/10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	      8q,/9d,9q,/10d,10q)
	  to (  1, 13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,  8,17,  9,
	      16, 10,15,  11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74as823 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit D-FF/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,
	     8d,8q,9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,
	      7q,8d,8q,9d,9q)
	  to (  1,  11,    14, 13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,
	      17, 9,16,10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74as824 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit D-FF/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,
	     /7d,7q,/8d,8q,/9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,
	      6q,/7d,7q,/8d,8q,/9d,9q)
	  to (  1,  11,    14, 13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,
	      18,  8,17,  9,16, 10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74as825 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register noninv" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,
	     6d,6q,7d,7q,8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,
	      6d,6q,7d,7q,8d,8q)
	  to (   1,   2,  23,  11,    14, 13, 3,22, 4,21, 5,20, 6,19, 7,18,
	       8,17, 9,16,10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74as826 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,
	     5q,/6d,6q,/7d,7q,/8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,
	      /5d,5q,/6d,6q,/7d,7q,/8d,8q)
	  to (   1,   2,  23,  11,    14, 13,  3,22,  4,21,  5,20,  6,19,
	        7,18,  8,17,  9,16, 10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74as832 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input OR Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74as841 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	     10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	      10d,10q)
	  to (  1,13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,15,
	       11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74as842 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit Transparent Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,8q,
	     /9d,9q,/10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	      8q,/9d,9q,/10d,10q)
	  to (  1,13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,  8,17,  9,
	      16, 10,15,  11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74as843 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/pre,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,
	     8q,9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/pre, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,
	      8d,8q,9d,9q)
	  to (  1,  11,  14,13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17,
	       9,16,10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74as844 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit Transparent Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/pre,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,
	     7q,/8d,8q,/9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/pre, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,
	      /7d,7q,/8d,8q,/9d,9q)
	  to (  1,  14,  11,13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,
	        8,17,  9,16, 10,15) ;
	swap ( [  1,14,11,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74as845 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Latch noninv" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/pre,/clr,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,
	     6q,7d,7q,8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/pre,/clr, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,
	      6q,7d,7q,8d,8q)
	  to (   1,   2,  23,  14,  11,13, 3,22, 4,21, 5,20, 6,19, 7,18, 8,
	      17, 9,16,10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74as846 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/pre,/clr,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,
	     /6d,6q,/7d,7q,/8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/pre,/clr, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,
	      5q,/6d,6q,/7d,7q,/8d,8q)
	  to (   1,   2,  23,  14,  11,13,  3,22,  4,21,  5,20,  6,19,  7,
	      18,  8,17,  9,16, 10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74as850 : default so28,dil28b {
	newattr "$comment" = "16 to 1 Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,/gy,gw,clk,s0,s1,s2,s3,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,
	     d11,d12,d13,d14,d15,y,w) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat (/g,/gy,gw,clk,s0,s1,s2,s3,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,
	      d11,d12,d13,d14,d15, y, w)
	  to (10,  9,11, 12,18,17,16,15, 8, 7, 6, 5, 4, 3, 2, 1,27,26, 25,
	       24, 23, 22, 21, 20,19,13) ;
	}

part 74as851 : default so28,dil28b {
	newattr "$comment" = "16 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,/gy,gw,/sc,s0,s1,s2,s3,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,
	     d11,d12,d13,d14,d15,y,w) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat (/g,/gy,gw,/sc,s0,s1,s2,s3,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,
	      d11,d12,d13,d14,d15, y, w)
	  to (10,  9,11, 12,18,17,16,15, 8, 7, 6, 5, 4, 3, 2, 1,27,26, 25,
	       24, 23, 22, 21, 20,19,13) ;
	}

part 74as852 : default so24,dil24,dil24b {
	newattr "$comment" = "Universal Transceiver/Port Controller" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,s2,clk,serin,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,
	     a8,b8,q8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,clk,serin,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,
	      a8,b8,q8)
	  to ( 1, 2, 3, 23,   22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,15,
	      11,14,13) ;
	}

part 74as856 : default so24,dil24,dil24b {
	newattr "$comment" = "Universal Transceiver/Port Controller" ;
	newattr "$ttlout" = "TS" ;
	pin (/oeb,/oea,mode,clk,serin,a1,a2,b1,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8,q8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oeb,/oea,mode,clk,serin,a1,a2,b1,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8,q8)
	  to (   1,   2,   3, 23,   22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,
	      10,15,11,14,13) ;
	}

part 74as857 : default so24,dil24,dil24b {
	newattr "$comment" = "Hex 2 to 1 Universal Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,comp,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y,5a,5b,5y,6a,6b,
	     6y,"oper=0") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,comp,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y,5a,5b,5y,6a,
	      6b,6y,"oper=0")
	  to ( 1,23,  13, 2, 3, 4, 5, 6, 7, 8, 9,10,16,15,14,19,18,17,22,
	      21,20,      11) ;
	swap ( [  1,23,13,11,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       ( 8, 9,10),
	       (16,15,14),
	       (19,18,17),
	       (22,21,20) ] ) ;
	}

part 74as866 : default dil28b {
	newattr "$comment" = "8 Bit Magnitude Comp., Latched 8 Bit In" ;
	newattr "$ttlout" = "TP" ;
	pin ("l/a",ple,p0,p1,p2,p3,p4,p5,p6,p7,"ip>q","ip<q",ole,/clrq,qle,
	     q0,q1,q2,q3,q4,q5,q6,q7,"p>q","p<q","p=q") ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat ("l/a",ple,p0,p1,p2,p3,p4,p5,p6,p7,"ip>q","ip<q",ole,/clrq,qle,
	      q0,q1,q2,q3,q4,q5,q6,q7,"p>q","p<q","p=q")
	  to (    2, 26,18,19,20,21,22,23,24,25,     4,     3, 15,   27,  1,
	      12,11,10, 9, 8, 7, 6, 5,   16,   17,   13) ;
	}

part 74as867 : default so24,dil24,dil24b {
	newattr "$comment" = "8 Bit Synchronous Bidirectional Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,
	     h,qh) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,
	       h,qh)
	  to ( 1, 2,  11,  23, 14,  13,3,22,4,21,5,20,6,19,7,18,8,17,9,16,
	      10,15) ;
	}

part 74as869 : default so24,dil24,dil24b {
	newattr "$comment" = "8 Bit Synchronous Bidirectional Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,
	     h,qh) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,
	       h,qh)
	  to ( 1, 2,  11,  23, 14,  13,3,22,4,21,5,20,6,19,7,18,8,17,9,16,
	      10,15) ;
	}

part 74as870 : default dil24,dil24b {
	newattr "$comment" = "Dual 16 + 4 Register" ;
	newattr "$ttlout" = "TS" ;
	pin (1a0,1a1,1a2,1a3,2a0,2a1,2a2,2a3,s0,s1,s2,s3,/1w,/2w,dqa1,dqb1,
	     dqa2,dqb2,dqa3,dqb3,dqa4,dqb4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (1a0,1a1,1a2,1a3,2a0,2a1,2a2,2a3,s0,s1,s2,s3,/1w,/2w,dqa1,dqb1,
	      dqa2,dqb2,dqa3,dqb3,dqa4,dqb4)
	  to (  2,  3,  4,  5, 19, 20, 21, 22, 1,23, 7,17,  6, 18,   8,  13,
	         9,  14,  10,  15,  11,  16) ;
	}

part 74as871 : default dil28b {
	newattr "$comment" = "Dual 16 + 4 Register" ;
	newattr "$ttlout" = "TS" ;
	pin (1a0,1a1,1a2,1a3,2a0,2a1,2a2,2a3,s0,s1,s2,s3,/1w,/2w,da1,qa1,
	     dqb1,da2,qa2,dqb2,da3,qa3,dqb3,da4,qa4,dqb4) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat (1a0,1a1,1a2,1a3,2a0,2a1,2a2,2a3,s0,s1,s2,s3,/1w,/2w,da1,qa1,
	      dqb1,da2,qa2,dqb2,da3,qa3,dqb3,da4,qa4,dqb4)
	  to (  4,  5,  6,  7, 21, 22, 23, 24, 3,25, 9,19,  8, 20,  1, 10,
	        15,  2, 11,  16, 26, 12,  17, 27, 13,  18) ;
	}

part 74as873 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,/clr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,/clr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to (  2,23,   1, 3,22, 4,21, 5,20, 6,19)
	  or ( 11,14,  13, 7,18, 8,17, 9,16,10,15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74as874 : default so24,dil24,dil24b {
	newattr "$comment" = "Flip-Flop Octal D-Type" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to (  2, 23,   1, 3,22, 4,21, 5,20, 6,19)
	  or ( 11, 14,  13, 7,18, 8,17, 9,16,10,15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74as876 : default so24,dil24,dil24b {
	newattr "$comment" = "Flip-Flop Octal D-Type" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/pre,d1,/q1,d2,/q2,d3,/q3,d4,/q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/pre,d1,/q1,d2,/q2,d3,/q3,d4,/q4)
	  to (  2, 23,   1, 3, 22, 4, 21, 5, 20, 6, 19)
	  or ( 11, 14,  13, 7, 18, 8, 17, 9, 16,10, 15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74as877 : default dil24,dil24b {
	newattr "$comment" = "8 Bit Univ. Transceiver/Port Controller" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,s2,clk,serin,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,
	     a8,b8,q8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,clk,serin,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,
	      a8,b8,q8)
	  to ( 1, 2, 3, 23,   22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,15,
	      11,14,13) ;
	}

part 74as878 : default so24,dil24,dil24b {
	newattr "$comment" = "Dual 4 Bit D-FF, Edge Triggered noninv." ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to (  2, 23,   1, 3,22, 4,21, 5,20, 6,19)
	  or ( 11, 14,  13, 7,18, 8,17, 9,16,10,15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74as879 : default so24,dil24,dil24b {
	newattr "$comment" = "Dual 4 Bit D-FF, Triggered inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,d1,/q1,d2,/q2,d3,/q3,d4,/q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,d1,/q1,d2,/q2,d3,/q3,d4,/q4)
	  to (  2, 23,   1, 3, 22, 4, 21, 5, 20, 6, 19)
	  or ( 11, 14,  13, 7, 18, 8, 17, 9, 16,10, 15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74as880 : default so24,dil24,dil24b {
	newattr "$comment" = "Dual 4 Bit Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,/pre,d1,/q1,d2,/q2,d3,/q3,d4,/q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,/pre,d1,/q1,d2,/q2,d3,/q3,d4,/q4)
	  to (  2,23,   1, 3, 22, 4, 21, 5, 20, 6, 19)
	  or ( 11,14,  13, 7, 18, 8, 17, 9, 16,10, 15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74as881 : default so24,dil24,dil24b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to ( 6, 5, 4, 3,8, 7,15,17,   14,    16,  2,  1,  9, 23, 22, 10,
	       21, 20, 11, 19, 18, 13) ;
	}

part 74as882 : default so24,dil24,dil24b {
	newattr "$comment" = "32 Bit Look-Ahead Carry Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,/p4,/g4,/p5,/g5,/p6,/g6,/p7,
	     /g7,"cn+8","cn+16","cn+24","cn+32") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,/p4,/g4,/p5,/g5,/p6,/g6,
	      /p7,/g7,"cn+8","cn+16","cn+24","cn+32")
	  to ( 1,  3,  2,  5,  4,  8,  7, 10,  9, 14, 13, 16, 15, 19, 18,
	       21, 20,     6,     11,     17,     22) ;
	}

part 74as885 : default so24,dil24,dil24b {
	newattr "$comment" = "8 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin ("l/a",ple,p0,p1,p2,p3,p4,p5,p6,p7,"ip>q","ip<q",q0,q1,q2,q3,
	     q4,q5,q6,q7,"p>q","p<q") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat ("l/a",ple,p0,p1,p2,p3,p4,p5,p6,p7,"ip>q","ip<q",q0,q1,q2,q3,
	      q4,q5,q6,q7,"p>q","p<q")
	  to (    1, 23,15,16,17,18,19,20,21,22,     3,     2,11,10, 9, 8,
	       7, 6, 5, 4,   13,   14) ;
	}

part 74as1000 : default so14,dil14 {
	newattr "$comment" = "Buffered 00 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as1004 : default so14,dil14 {
	newattr "$comment" = "Buffered 04 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74as1005 : default so14,dil14 {
	newattr "$comment" = "Buffered 05 (24mA IOL)" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74as1008 : default so14,dil14 {
	newattr "$comment" = "Buffered 08 (24mA IOL)" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as1032 : default so14,dil14 {
	newattr "$comment" = "Buffered 32 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as1034 : default so14,dil14 {
	newattr "$comment" = "Buffered 34 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74as1036 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Positive NOR" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74as1804 : default dil20 {
	newattr "$comment" = "804 with Center Pinning" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (15) ;
	net "vcc" : (5) ;
	xlat ( a, b, y)
	  to ( 6, 7, 8)
	  or ( 9,10,11)
	  or (12,13,14)
	  or (17,18,16)
	  or (20, 1,19)
	  or ( 3, 4, 2) ;
	swap ( (( 6, 7), 8),
	       (( 9,10),11),
	       ((12,13),14),
	       ((17,18),16),
	       ((20, 1),19),
	       (( 3, 4), 2) ) ;
	}

part 74as1808 : default dil20 {
	newattr "$comment" = "808 with Center Pinning" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (15) ;
	net "vcc" : (5) ;
	xlat ( a, b, y)
	  to ( 6, 7, 8)
	  or ( 9,10,11)
	  or (12,13,14)
	  or (17,18,16)
	  or (20, 1,19)
	  or ( 3, 4, 2) ;
	swap ( (( 6, 7), 8),
	       (( 9,10),11),
	       ((12,13),14),
	       ((17,18),16),
	       ((20, 1),19),
	       (( 3, 4), 2) ) ;
	}

part 74as1832 : default dil20 {
	newattr "$comment" = "832 with Center Pinning" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (15) ;
	net "vcc" : (5) ;
	xlat ( a, b, y)
	  to ( 6, 7, 8)
	  or ( 9,10,11)
	  or (12,13,14)
	  or (17,18,16)
	  or (20, 1,19)
	  or ( 3, 4, 2) ;
	swap ( (( 6, 7), 8),
	       (( 9,10),11),
	       ((12,13),14),
	       ((17,18),16),
	       ((20, 1),19),
	       (( 3, 4), 2) ) ;
	}

part 74as2620 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Trcv./MOS Driver inverting" ;
	newattr "$ttlout" = "RT" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as2623 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Trcv./MOS Driver noninverting" ;
	newattr "$ttlout" = "RT" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as2640 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Trcv./MOS Driver inverting" ;
	newattr "$ttlout" = "RT" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74as2645 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Trcv./MOS Driver noninverting" ;
	newattr "$ttlout" = "RT" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.