loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d74als.def                                */
/* SCM Library   : d74als.ddb                                */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - Bipolar TTL Advanced Low Power Schottky / Series 74ALS  */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 74  = Commercial (0..70 Degree Celcius)   */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 74als00 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als01 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74als02 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74als03 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als04 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74als05 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74als08 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als09 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als10 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74als11 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74als12 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74als15 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74als20 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74als21 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74als22 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74als27 : default so14,dil14 {
	newattr "$comment" = "Triple 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74als28 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74als30 : default so14,dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 74als32 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als33 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74als34 : default so14,dil14 {
	newattr "$comment" = "Hex Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74als35 : default so14,dil14 {
	newattr "$comment" = "Hex Buffer" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74als37 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als38 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als40 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74als74 : default so14,dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 74als86 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als109 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,/k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk,/k,/clr, q,/q)
	  to (   5, 2,  4, 3,   1, 6, 7)
	  or (  11,14, 12,13,  15,10, 9) ;
	swap ( ( 5, 2, 4, 3, 1, 6, 7), (11,14,12,13,15,10, 9) ) ;
	}

part 74als112 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   4, 3,  1, 2,  15,5, 6)
	  or (  10,11, 13,12,  14,9, 7) ;
	swap ( ( 4, 3, 1, 2,15, 5, 6), (10,11,13,12,14, 9, 7) ) ;
	}

part 74als113 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre, j,clk, k,q,/q)
	  to (   4, 3,  1, 2,5, 6)
	  or (  10,11, 13,12,9, 8) ;
	swap ( ( 4, 3, 1, 2, 5, 6), (10,11,13,12, 9, 8) ) ;
	}

part 74als114 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (   1, 13,    4, 3, 2, 5,  6,   10,11,12, 9,  8) ;
	swap ( [  1,13, ( 4, 3, 2, 5, 6), (10,11,12, 9, 8) ] ) ;
	}

part 74als123 : default so16,dil16 {
	newattr "$comment" = "Dual Monostable Multivibrator, Retrigg." ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/clr,cx,rx,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,rx, q,/q)
	  to (1, 2,   3,14,15,13, 4)
	  or (9,10,  11, 6, 7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 74als131 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder, Address Registers" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (  4,1,2,3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 74als133 : default so16,dil16 {
	newattr "$comment" = "13 Input Positive NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,k,l,m,y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,d,e,f,g, h, i, j, k, l, m,y)
	  to (1,2,3,4,5,6,7,10,11,12,13,14,15,9) ;
	swap ( (( 1, 2, 3, 4, 5, 6, 7,10,11,12,13,14,15), 9) ) ;
	}

part 74als136 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als137 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder, Address Registers" ;
	newattr "$ttlout" = "TP" ;
	pin (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (  4,1,2,3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 74als138 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (1,2,3, 6,   4,   5,15,14,13,12,11,10, 9, 7) ;
	swap internal ( (( 4, 5)) ) ;
	}

part 74als139 : default so16,dil16 {
	newattr "$comment" = "Dual 2 of 4 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,/g,y0,y1,y2,y3)
	  to ( 2, 3, 1, 4, 5, 6, 7)
	  or (14,13,15,12,11,10, 9) ;
	swap ( ( 2, 3, 1, 4, 5, 6, 7), (14,13,15,12,11,10, 9) ) ;
	}

part 74als151 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74als153 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74als154 : default dil24,dil24b {
	newattr "$comment" = "4 of 16 Line Decoder/Demultiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,
	     y14,y15) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat ( a, b, c, d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,
	      y13,y14,y15)
	  to (23,22,21,20, 18, 19, 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 13, 14,
	       15, 16, 17) ;
	swap internal ( ((18,19)) ) ;
	}

part 74als155 : default so16,dil16 {
	newattr "$comment" = "Dual 1 of 4 Decoder/Demultiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3)
	  to (13, 3,  2, 1,  7,  6,  5,  4, 14, 15,  9, 10, 11, 12) ;
	}

part 74als156 : default so16,dil16 {
	newattr "$comment" = "Dual 1 of 4 Decoder/Demultiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3)
	  to (13, 3,  2, 1,  7,  6,  5,  4, 14, 15,  9, 10, 11, 12) ;
	}

part 74als157 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74als158 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74als160 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74als161 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74als162 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74als163 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74als164 : default so14,dil14 {
	newattr "$comment" = "8 Bit Shift Register SIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh)
	  to (   9,  8,1,2, 3, 4, 5, 6,10,11,12,13) ;
	swap internal ( (( 1, 2)) ) ;
	}

part 74als165 : default so16,dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh,/qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (shld,clkinh,clk,ser, a, b, c, d,e,f,g,h,qh,/qh)
	  to (   1,    15,  2, 10,11,12,13,14,3,4,5,6, 9,  7) ;
	}

part 74als166 : default so16,dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clkinh,clk,ser,a,b,c,d, e, f, g, h,qh)
	  to (   9,  15,     6,  7,  1,2,3,4,5,10,11,12,14,13) ;
	}

part 74als168 : default dil16 {
	newattr "$comment" = "4 Bit Decade Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74als169 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74als174 : default so16,dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,d2,q2,d3,d4,q3,q4,d5,q5,d6,q6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,d2,q2,d3,q3,d4,q4,d5,q5,d6,q6)
	  to (   1,  9, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  1, 9,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 74als175 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (   1,  9, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  1, 9,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 74als190 : default so16,dil16 {
	newattr "$comment" = "Synchronous Up/Down BCD Counter" ;
	newattr "$ttlout" = "OC" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74als191 : default so16,dil16 {
	newattr "$comment" = "Synchronous Up/Down Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74als192 : default so16,dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock BCD Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74als193 : default so16,dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74als230 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2,2a3,
	     2y3,2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (/2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to ( 19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als231 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als240 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als241 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als242 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74als243 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74als244 : default so20,dil20 {
	newattr "$comment" = "Octal Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als245 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als251 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74als253 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74als257 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74als258 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74als259 : default so16,dil16 {
	newattr "$comment" = "8 Bit Addressable Set-Reset Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,/g,d,/clr,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (s0,s1,s2,/g, d,/clr,q0,q1,q2,q3,q4,q5,q6,q7)
	  to ( 1, 2, 3,14,13,  15, 4, 5, 6, 7, 9,10,11,12) ;
	}

part 74als264 : default so16,dil16 {
	newattr "$comment" = "Counter Look-Ahead" ;
	newattr "$ttlout" = "TP" ;
	pin (ce,b0,a0,b1,a1,b2,a2,b3,a3,c0,c1,c2,rcoa,rcob) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ce,b0,a0,b1,a1,b2,a2,b3,a3,c0,c1,c2,rcoa,rcob)
	  to (13, 4, 3, 2, 1,15,14, 6, 5,12,11, 9,  10,   7) ;
	}

part 74als273 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (   1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74als280 : default so14,dil14 {
	newattr "$comment" = "9 Bit Odd/Even Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,even,odd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,even,odd)
	  to (8,9,10,11,12,13,1,2,4,   5,  6) ;
	swap ( (( 8, 9,10,11,12,13, 1, 2, 4), 5, 6) ) ;
	}

part 74als286 : default so14,dil14 {
	newattr "$comment" = "9 Bit Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,/xmit,pario,parerr) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,/xmit,pario,parerr)
	  to (8,9,10,11,12,13,1,2,4,    3,    6,     5) ;
	swap internal ( (( 8, 9,10,11,12,13, 1, 2, 4)) ) ;
	}

part 74als298 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer, Storage" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd)
	  to (10, 11, 3, 2,15, 4, 1,14, 9, 5,13, 7, 6,12) ;
	swap ( [ 10,11,
	       ( 3, 2,15),
	       ( 4, 1,14),
	       ( 9, 5,13),
	       ( 7, 6,12) ] ) ;
	}

part 74als299 : default so20,dil20 {
	newattr "$comment" = "8 Bit Universal PIPO Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74als323 : default so20,dil20 {
	newattr "$comment" = "8 Bit Shift/Storage Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74als352 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74als353 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74als354 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74als355 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74als356 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74als357 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74als365 : default so16,dil16 {
	newattr "$comment" = "Hex Buffer W/Common Enable" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	swap internal ( (( 1,15)) ) ;
	}

part 74als366 : default so16,dil16 {
	newattr "$comment" = "Hex Inverter W/Common Enable" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	swap internal ( (( 1,15)) ) ;
	}

part 74als367 : default so16,dil16 {
	newattr "$comment" = "Hex Buffer 4 Bit and 2 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2,  3,  4,  5,  6,  7, 10,  9) ;
	xlat (/2g,2a1,2y1,2a2,2y2)
	  to ( 15, 12, 11, 14, 13) ;
	swap internal ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), (10, 9) ] ) ;
	swap internal ( [ 15, (12,11), (14,13) ] ) ;
	}

part 74als368 : default so16,dil16 {
	newattr "$comment" = "Hex Inverter 4 Bit and 2 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2,  3,  4,  5,  6,  7, 10,  9) ;
	xlat (/2g,2a1,2y1,2a2,2y2)
	  to ( 15, 12, 11, 14, 13) ;
	swap internal ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), (10, 9) ] ) ;
	swap internal ( [ 15, (12,11), (14,13) ] ) ;
	}

part 74als373 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74als374 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74als377 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop with Data Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to ( 11, 1, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [ 11, 1,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74als396 : default so16,dil16 {
	newattr "$comment" = "Octal Storage Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,clk,d1,1q1,2q1,d2,1q2,2q2,d3,1q3,2q3,d4,1q4,2q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,clk,d1,1q1,2q1,d2,1q2,2q2,d3,1q3,2q3,d4,1q4,2q4)
	  to (15,  7, 3,  2,  1, 6,  5,  4, 9, 10, 11,12, 13, 14) ;
	swap ( [ 15, 7,
	       ( 3, 2, 1),
	       ( 6, 5, 4),
	       ( 9,10,11),
	       (12,13,14) ] ) ;
	}

part 74als465 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer Gate Enabled noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2, 3, 4, 5, 6, 7, 8, 9,12,11,14,13,16,15,18,17) ;
	swap ( [  1,19,
	       ( 2, 3),
	       ( 4, 5),
	       ( 6, 7),
	       ( 8, 9),
	       (12,11),
	       (14,13),
	       (16,15),
	       (18,17) ] ) ;
	}

part 74als466 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer Gate Enabled inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2, 3, 4, 5, 6, 7, 8, 9,12,11,14,13,16,15,18,17) ;
	swap ( [  1,19,
	       ( 2, 3),
	       ( 4, 5),
	       ( 6, 7),
	       ( 8, 9),
	       (12,11),
	       (14,13),
	       (16,15),
	       (18,17) ] ) ;
	}

part 74als467 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer Gated Enable noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2, 3, 4, 5, 6, 7, 8, 9)
	  or (19,12,11,14,13,16,15,18,17) ;
	swap ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), ( 8, 9) ],
	       [ 19, (12,11), (14,13), (16,15), (18,17) ] ) ;
	}

part 74als468 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer Gated Enable inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2, 3, 4, 5, 6, 7, 8, 9)
	  or (19,12,11,14,13,16,15,18,17) ;
	swap ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), ( 8, 9) ],
	       [ 19, (12,11), (14,13), (16,15), (18,17) ] ) ;
	}

part 74als518 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,   19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74als519 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,   19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74als520 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74als521 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74als522 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74als526 : default so20,dil20 {
	newattr "$comment" = "16 Bit Fuse-Programmable Identity Comp." ;
	newattr "$ttlout" = "TP" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,/g,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,/g,"/p=q")
	  to ( 2, 3, 4, 5, 6, 7, 8, 9,11,12, 13, 14, 15, 16, 17, 18, 1,    19) ;
	}

part 74als527 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity, 4 Bit Fuse-Progr. Comp." ;
	newattr "$ttlout" = "TP" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,/g,p8,p9,p10,p11,q8,q9,q10,q11,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,/g,p8,p9,p10,p11,q8,q9,q10,q11,"/p=q")
	  to ( 2, 3, 4, 5, 6, 7, 8, 9, 1,11,13, 15, 17,12,14, 16, 18,    19) ;
	swap internal ( ((11,12),(13,14),(15,16),(17,18)) ) ;
	}

part 74als528 : default so16,dil16 {
	newattr "$comment" = "12 Bit Fuse-Programmable Identity Comp." ;
	newattr "$ttlout" = "TP" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,/g,"/p=q") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,/g,"/p=q")
	  to ( 2, 3, 4, 5, 6, 7, 9,10,11,12, 13, 14, 1,    15) ;
	}

part 74als533 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74als534 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74als538 : default so20,dil20 {
	newattr "$comment" = "3 of 8 Decoder" ;
	newattr "$ttlout" = "TS" ;
	pin (al,/oe1,/oe2,a,b,c,g1,g2,/g3,/g4,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (al,/oe1,/oe2,a,b, c,g1,g2,/g3,/g4,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (12,   4,   5,6,7,17,13,14, 15, 16, 3, 2, 1,19,18, 8, 9,11) ;
	swap internal ( (( 4, 5)) ) ;
	swap internal ( ((13,14)) ) ;
	swap internal ( ((15,16)) ) ;
	}

part 74als539 : default so20,dil20 {
	newattr "$comment" = "Dual 1 of 4 Decoder" ;
	newattr "$ttlout" = "TS" ;
	pin (al,/oe,a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (al,/oe, a, b,/g,y0,y1,y2,y3)
	  to ( 4,  5,17,18,16, 3, 2, 1,19)
	  or (13, 14, 6, 7,15,12,11, 9, 8) ;
	swap ( ( 4, 5,17,18,16, 3, 2, 1,19),
	       (13,14, 6, 7,15,12,11, 9, 8) ) ;
	}

part 74als540 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74als541 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74als560 : default so20,dil20 {
	newattr "$comment" = "4 Bit Decade Counter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ent,enp,/sclr,/sload,clk,/aclr,/aload,cco,rco,a,qa,b,qb,c,
	     qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,ent,enp,/sclr,/sload,clk,/aclr,/aload,cco,rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (17, 12,  7,    9,    11,  2,    8,     1, 18, 19,3,16,4,15,
	      5,14,6,13) ;
	}

part 74als561 : default so20,dil20 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ent,enp,/sclr,/sload,clk,/aclr,/aload,cco,rco,a,qa,b,qb,c,
	     qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,ent,enp,/sclr,/sload,clk,/aclr,/aload,cco,rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (17, 12,  7,    9,    11,  2,    8,     1, 18, 19,3,16,4,15,
	      5,14,6,13) ;
	}

part 74als563 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74als564 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74als568 : default dil20 {
	newattr "$comment" = "4 Bit Decade Counter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (17,    1,  2,  12,   7,    9,   11,    8,  18,  19,3,16,4,15,
	      5,14,6,13) ;
	}

part 74als569 : default dil20 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (17,    1,  2,  12,   7,    9,   11,    8,  18,  19,3,16,4,15,
	      5,14,6,13) ;
	}

part 74als573 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 2,19, 3,18, 4,17, 5,16, 6,15, 7,14, 8,13, 9,12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74als574 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop (Data Flow Thru 374)" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 2,19, 3,18, 4,17, 5,16, 6,15, 7,14, 8,13, 9,12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74als575 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal D-Flip-Flop (574 with Clear)" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  2, 14,   1, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,15) ;
	swap ( [  2,14, 1,
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74als576 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74als577 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal D-Flip-Flop (576 with Clear)" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,
	     8d,/8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,
	      8d,/8q)
	  to (  2, 14,   1, 3, 22, 4, 21, 5, 20, 6, 19, 7, 18, 8, 17, 9, 16,
	      10, 15) ;
	swap ( [  2,14, 1,
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74als580 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 2, 19, 3, 18, 4, 17, 5, 16, 6, 15, 7, 14, 8, 13, 9,
	       12) ;
	swap ( [  1,11,
	       ( 2,19),
	       ( 3,18),
	       ( 4,17),
	       ( 5,16),
	       ( 6,15),
	       ( 7,14),
	       ( 8,13),
	       ( 9,12) ] ) ;
	}

part 74als616 : default dil40 {
	newattr "$comment" = "16 Bit Parallel Error Detect/Correct" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	     db11,db12,db13,db14,db15,cb0,cb1,cb2,cb3,cb4,cb5,/oeb0,/oeb1,
	     /oecb,/ledbo) ;
	net "vss" : (34) ;
	net "vcc" : (40) ;
	xlat (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	      db11,db12,db13,db14,db15,cb0,cb1,cb2,cb3,cb4,cb5,/oeb0,/oeb1,
	      /oecb,/ledbo)
	  to (38,39,   3,    2,  9, 10, 12, 13, 14, 15, 16, 17, 25, 26,  27,
	        28,  29,  30,  32,  33, 24, 23, 22, 21, 19, 18,   11,   31,
	         20,     1) ;
	}

part 74als617 : default dil40 {
	newattr "$comment" = "16 Bit Parallel Error Detect/Correct" ;
	newattr "$ttlout" = "OC" ;
	pin (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	     db11,db12,db13,db14,db15,cb0,cb1,cb2,cb3,cb4,cb5,/oeb0,/oeb1,
	     /oecb,/ledbo) ;
	net "vss" : (34) ;
	net "vcc" : (40) ;
	xlat (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	      db11,db12,db13,db14,db15,cb0,cb1,cb2,cb3,cb4,cb5,/oeb0,/oeb1,
	      /oecb,/ledbo)
	  to (38,39,   3,    2,  9, 10, 12, 13, 14, 15, 16, 17, 25, 26,  27,
	        28,  29,  30,  32,  33, 24, 23, 22, 21, 19, 18,   11,   31,
	         20,     1) ;
	}

part 74als620 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als621 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als622 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als623 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als632 : default dil52 {
	newattr "$comment" = "32 Bit Error Detect/Correct, Byte Write" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	     db11,db12,db13,db14,db15,db16,db17,db18,db19,db20,db21,db22,
	     db23,db24,db25,db26,db27,db28,db29,db30,db31,cb0,cb1,cb2,cb3,
	     cb4,cb5,cb6,/oeb0,/oeb1,/oeb2,/oeb3,/oecb,/ledbo) ;
	net "vss" : (13,40) ;
	net "vcc" : (52) ;
	xlat (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	      db11,db12,db13,db14,db15,db16,db17,db18,db19,db20,db21,db22,
	      db23,db24,db25,db26,db27,db28,db29,db30,db31,cb0,cb1,cb2,cb3,
	      cb4,cb5,cb6,/oeb0,/oeb1,/oeb2,/oeb3,/oecb,/ledbo)
	  to (50,51,   3,    2,  4,  5,  6,  7,  8,  9, 11, 12, 14, 15,  17,
	        18,  19,  20,  21,  22,  31,  32,  33,  34,  35,  36,  38,
	        39,  41,  42,  44,  45,  46,  47,  48,  49, 30, 29, 28, 27,
	       25, 24, 23,   10,   16,   37,   43,   26,     1) ;
	}

part 74als633 : default dil52 {
	newattr "$comment" = "32 Bit Error Detect/Correct, Byte Write" ;
	newattr "$ttlout" = "OC" ;
	pin (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	     db11,db12,db13,db14,db15,db16,db17,db18,db19,db20,db21,db22,
	     db23,db24,db25,db26,db27,db28,db29,db30,db31,cb0,cb1,cb2,cb3,
	     cb4,cb5,cb6,/oeb0,/oeb1,/oeb2,/oeb3,/oecb,/ledbo) ;
	net "vss" : (13,40) ;
	net "vcc" : (52) ;
	xlat (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	      db11,db12,db13,db14,db15,db16,db17,db18,db19,db20,db21,db22,
	      db23,db24,db25,db26,db27,db28,db29,db30,db31,cb0,cb1,cb2,cb3,
	      cb4,cb5,cb6,/oeb0,/oeb1,/oeb2,/oeb3,/oecb,/ledbo)
	  to (50,51,   3,    2,  4,  5,  6,  7,  8,  9, 11, 12, 14, 15,  17,
	        18,  19,  20,  21,  22,  31,  32,  33,  34,  35,  36,  38,
	        39,  41,  42,  44,  45,  46,  47,  48,  49, 30, 29, 28, 27,
	       25, 24, 23,   10,   16,   37,   43,   26,     1) ;
	}

part 74als634 : default dil48 {
	newattr "$comment" = "32 Bit Error Detect/Correct" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	     db11,db12,db13,db14,db15,db16,db17,db18,db19,db20,db21,db22,
	     db23,db24,db25,db26,db27,db28,db29,db30,db31,cb0,cb1,cb2,cb3,
	     cb4,cb5,cb6,/oecb,/oedb) ;
	net "vss" : (12,37) ;
	net "vcc" : (48) ;
	xlat (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	      db11,db12,db13,db14,db15,db16,db17,db18,db19,db20,db21,db22,
	      db23,db24,db25,db26,db27,db28,db29,db30,db31,cb0,cb1,cb2,cb3,
	      cb4,cb5,cb6,/oecb,/oedb)
	  to (46,47,   2,    1,  3,  4,  5,  6,  7,  8, 10, 11, 13, 14,  15,
	        16,  17,  18,  19,  20,  29,  30,  31,  32,  33,  34,  35,
	        36,  38,  39,  40,  41,  42,  43,  44,  45, 28, 27, 26, 25,
	       23, 22, 21,   24,    9) ;
	}

part 74als635 : default dil48 {
	newattr "$comment" = "32 Bit Error Detect/Correct" ;
	newattr "$ttlout" = "OC" ;
	pin (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	     db11,db12,db13,db14,db15,db16,db17,db18,db19,db20,db21,db22,
	     db23,db24,db25,db26,db27,db28,db29,db30,db31,cb0,cb1,cb2,cb3,
	     cb4,cb5,cb6,/oecb,/oedb) ;
	net "vss" : (12,37) ;
	net "vcc" : (48) ;
	xlat (s0,s1,/err,/merr,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	      db11,db12,db13,db14,db15,db16,db17,db18,db19,db20,db21,db22,
	      db23,db24,db25,db26,db27,db28,db29,db30,db31,cb0,cb1,cb2,cb3,
	      cb4,cb5,cb6,/oecb,/oedb)
	  to (46,47,   2,    1,  3,  4,  5,  6,  7,  8, 10, 11, 13, 14,  15,
	        16,  17,  18,  19,  20,  29,  30,  31,  32,  33,  34,  35,
	        36,  38,  39,  40,  41,  42,  43,  44,  45, 28, 27, 26, 25,
	       23, 22, 21,   24,    9) ;
	}

part 74als638 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als639 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als640 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als641 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als642 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als643 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver true inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als644 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als645 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als646 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74als647 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74als648 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74als649 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74als651 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74als652 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74als653 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74als654 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74als677 : default so24,dil24,dil24b {
	newattr "$comment" = "16 to 4 Bit Address Comparator, Enable" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,p0,p1,p2,p3,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,
	     a15,a16,y) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,p0,p1,p2,p3,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,
	      a15,a16, y)
	  to (23,18,19,20,21, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15,
	       16, 17,22) ;
	}

part 74als678 : default so24,dil24,dil24b {
	newattr "$comment" = "16 to 4 Bit Address Comparator, Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (c,p0,p1,p2,p3,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,
	     a15,a16,y) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat ( c,p0,p1,p2,p3,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,
	      a15,a16, y)
	  to (23,18,19,20,21, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15,
	       16, 17,22) ;
	}

part 74als679 : default so20,dil20 {
	newattr "$comment" = "12 to 4 Bit Address Comparator, Enable" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,p0,p1,p2,p3,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12, y)
	  to (19,14,15,16,17, 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13,18) ;
	}

part 74als680 : default so20,dil20 {
	newattr "$comment" = "12 to 4 Bit Address Comparator, Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (c,p0,p1,p2,p3,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( c,p0,p1,p2,p3,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12, y)
	  to (19,14,15,16,17, 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13,18) ;
	}

part 74als688 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator, Output Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74als689 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator, Output Enable" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 74als746 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer, Input Resistor inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74als747 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer, Input Resistor noninv." ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74als756 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Driver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als757 : default dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als758 : default so14,dil14 {
	newattr "$comment" = "Quad Transceiver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74als759 : default so14,dil14 {
	newattr "$comment" = "Quad Transceiver noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74als760 : default dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als762 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2,2a3,
	     2y3,2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (/2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to ( 19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als763 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Driver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als804 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input NAND Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74als805 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input NOR Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74als808 : default dil20 {
	newattr "$comment" = "Hex 2 Input AND Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74als810 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als811 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive NOR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als821 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit D-FF/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	     10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,
	      9q,10d,10q)
	  to (  1, 13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,
	      15, 11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74als822 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit D-FF/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	     8q,/9d,9q,/10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	      8q,/9d,9q,/10d,10q)
	  to (  1, 13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,  8,17,  9,
	      16, 10,15,  11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74als823 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit D-FF/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,
	     8d,8q,9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,
	      7q,8d,8q,9d,9q)
	  to (  1,  11,    14, 13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,
	      17, 9,16,10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74als824 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit D-FF/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,
	     /7d,7q,/8d,8q,/9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,
	      6q,/7d,7q,/8d,8q,/9d,9q)
	  to (  1,  11,    14, 13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,
	      18,  8,17,  9,16, 10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74als825 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register noninv" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,
	     6d,6q,7d,7q,8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,
	      6d,6q,7d,7q,8d,8q)
	  to (   1,   2,  23,  11,    14, 13, 3,22, 4,21, 5,20, 6,19, 7,18,
	       8,17, 9,16,10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74als826 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,
	     5q,/6d,6q,/7d,7q,/8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,
	      /5d,5q,/6d,6q,/7d,7q,/8d,8q)
	  to (   1,   2,  23,  11,    14, 13,  3,22,  4,21,  5,20,  6,19,
	        7,18,  8,17,  9,16, 10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74als832 : default so20,dil20 {
	newattr "$comment" = "Hex 2 Input OR Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 7, 8, 9)
	  or (12,13,11)
	  or (15,16,14)
	  or (18,19,17) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 7, 8), 9),
	       ((12,13),11),
	       ((15,16),14),
	       ((18,19),17) ) ;
	}

part 74als841 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	     10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	      10d,10q)
	  to (  1,13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17, 9,16,10,15,
	       11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74als842 : default so24,dil24,dil24b {
	newattr "$comment" = "10 Bit Transparent Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,8q,
	     /9d,9q,/10d,10q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	      8q,/9d,9q,/10d,10q)
	  to (  1,13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,  8,17,  9,
	      16, 10,15,  11, 14) ;
	swap ( [  1,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15),
	       (11,14) ] ) ;
	}

part 74als843 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/pre,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,
	     8q,9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/pre, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,
	      8d,8q,9d,9q)
	  to (  1,  11,  14,13, 2,23, 3,22, 4,21, 5,20, 6,19, 7,18, 8,17,
	       9,16,10,15) ;
	swap ( [  1,11,14,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74als844 : default so24,dil24,dil24b {
	newattr "$comment" = "9 Bit Transparent Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,/clr,/pre,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,
	     7q,/8d,8q,/9d,9q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,/clr,/pre, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,
	      /7d,7q,/8d,8q,/9d,9q)
	  to (  1,  14,  11,13,  2,23,  3,22,  4,21,  5,20,  6,19,  7,18,
	        8,17,  9,16, 10,15) ;
	swap ( [  1,14,11,13,
	       ( 2,23),
	       ( 3,22),
	       ( 4,21),
	       ( 5,20),
	       ( 6,19),
	       ( 7,18),
	       ( 8,17),
	       ( 9,16),
	       (10,15) ] ) ;
	}

part 74als845 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Latch noninv" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/pre,/clr,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,
	     6q,7d,7q,8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/pre,/clr, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,
	      6q,7d,7q,8d,8q)
	  to (   1,   2,  23,  14,  11,13, 3,22, 4,21, 5,20, 6,19, 7,18, 8,
	      17, 9,16,10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74als846 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc1,/oc2,/oc3,/pre,/clr,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,
	     /6d,6q,/7d,7q,/8d,8q) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc1,/oc2,/oc3,/pre,/clr, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,
	      5q,/6d,6q,/7d,7q,/8d,8q)
	  to (   1,   2,  23,  14,  11,13,  3,22,  4,21,  5,20,  6,19,  7,
	      18,  8,17,  9,16, 10,15) ;
	swap internal ( (( 1, 2,23)) ) ;
	swap internal ( ( 3,22),
	                ( 4,21),
	                ( 5,20),
	                ( 6,19),
	                ( 7,18),
	                ( 8,17),
	                ( 9,16),
	                (10,15) ) ;
	}

part 74als857 : default so24,dil24,dil24b {
	newattr "$comment" = "Hex 2 to 1 Universal Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,comp,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y,5a,5b,5y,6a,6b,
	     6y,"oper=0") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,comp,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y,5a,5b,5y,6a,
	      6b,6y,"oper=0")
	  to ( 1,23,  13, 2, 3, 4, 5, 6, 7, 8, 9,10,16,15,14,19,18,17,22,
	      21,20,      11) ;
	swap ( [  1,23,13,11,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       ( 8, 9,10),
	       (16,15,14),
	       (19,18,17),
	       (22,21,20) ] ) ;
	}

part 74als867 : default so24,dil24,dil24b {
	newattr "$comment" = "8 Bit Synchronous Bidirectional Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,
	     h,qh) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,
	       h,qh)
	  to ( 1, 2,  11,  23, 14,  13,3,22,4,21,5,20,6,19,7,18,8,17,9,16,
	      10,15) ;
	}

part 74als869 : default so24,dil24,dil24b {
	newattr "$comment" = "8 Bit Synchronous Bidirectional Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,
	     h,qh) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd,e,qe,f,qf,g,qg,
	       h,qh)
	  to ( 1, 2,  11,  23, 14,  13,3,22,4,21,5,20,6,19,7,18,8,17,9,16,
	      10,15) ;
	}

part 74als870 : default dil24,dil24b {
	newattr "$comment" = "Dual 16 + 4 Register" ;
	newattr "$ttlout" = "TS" ;
	pin (1a0,1a1,1a2,1a3,2a0,2a1,2a2,2a3,s0,s1,s2,s3,/1w,/2w,dqa1,dqb1,
	     dqa2,dqb2,dqa3,dqb3,dqa4,dqb4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (1a0,1a1,1a2,1a3,2a0,2a1,2a2,2a3,s0,s1,s2,s3,/1w,/2w,dqa1,dqb1,
	      dqa2,dqb2,dqa3,dqb3,dqa4,dqb4)
	  to (  2,  3,  4,  5, 19, 20, 21, 22, 1,23, 7,17,  6, 18,   8,  13,
	         9,  14,  10,  15,  11,  16) ;
	}

part 74als871 : default dil28b {
	newattr "$comment" = "Dual 16 + 4 Register" ;
	newattr "$ttlout" = "TS" ;
	pin (1a0,1a1,1a2,1a3,2a0,2a1,2a2,2a3,s0,s1,s2,s3,/1w,/2w,da1,qa1,
	     dqb1,da2,qa2,dqb2,da3,qa3,dqb3,da4,qa4,dqb4) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat (1a0,1a1,1a2,1a3,2a0,2a1,2a2,2a3,s0,s1,s2,s3,/1w,/2w,da1,qa1,
	      dqb1,da2,qa2,dqb2,da3,qa3,dqb3,da4,qa4,dqb4)
	  to (  4,  5,  6,  7, 21, 22, 23, 24, 3,25, 9,19,  8, 20,  1, 10,
	        15,  2, 11,  16, 26, 12,  17, 27, 13,  18) ;
	}

part 74als873 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,/clr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,/clr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to (  2,23,   1, 3,22, 4,21, 5,20, 6,19)
	  or ( 11,14,  13, 7,18, 8,17, 9,16,10,15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74als874 : default so24,dil24,dil24b {
	newattr "$comment" = "Flip-Flop Octal D-Type" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to (  2, 23,   1, 3,22, 4,21, 5,20, 6,19)
	  or ( 11, 14,  13, 7,18, 8,17, 9,16,10,15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74als876 : default so24,dil24,dil24b {
	newattr "$comment" = "Flip-Flop Octal D-Type" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/pre,d1,/q1,d2,/q2,d3,/q3,d4,/q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/pre,d1,/q1,d2,/q2,d3,/q3,d4,/q4)
	  to (  2, 23,   1, 3, 22, 4, 21, 5, 20, 6, 19)
	  or ( 11, 14,  13, 7, 18, 8, 17, 9, 16,10, 15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74als878 : default so24,dil24,dil24b {
	newattr "$comment" = "Dual 4 Bit D-FF, Edge Triggered noninv." ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to (  2, 23,   1, 3,22, 4,21, 5,20, 6,19)
	  or ( 11, 14,  13, 7,18, 8,17, 9,16,10,15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74als879 : default so24,dil24,dil24b {
	newattr "$comment" = "Dual 4 Bit D-FF, Triggered inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,/clr,d1,/q1,d2,/q2,d3,/q3,d4,/q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc,clk,/clr,d1,/q1,d2,/q2,d3,/q3,d4,/q4)
	  to (  2, 23,   1, 3, 22, 4, 21, 5, 20, 6, 19)
	  or ( 11, 14,  13, 7, 18, 8, 17, 9, 16,10, 15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74als880 : default so24,dil24,dil24b {
	newattr "$comment" = "Dual 4 Bit Transparent Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,/pre,d1,/q1,d2,/q2,d3,/q3,d4,/q4) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/oc, c,/pre,d1,/q1,d2,/q2,d3,/q3,d4,/q4)
	  to (  2,23,   1, 3, 22, 4, 21, 5, 20, 6, 19)
	  or ( 11,14,  13, 7, 18, 8, 17, 9, 16,10, 15) ;
	swap ( [  2,23, 1, ( 3,22), ( 4,21), ( 5,20), ( 6,19) ],
	       [ 11,14,13, ( 7,18), ( 8,17), ( 9,16), (10,15) ] ) ;
	}

part 74als1000 : default so14,dil14 {
	newattr "$comment" = "Buffered 00 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als1002 : default so14,dil14 {
	newattr "$comment" = "Buffered 02 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74als1003 : default so14,dil14 {
	newattr "$comment" = "Buffered 03 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als1004 : default so14,dil14 {
	newattr "$comment" = "Buffered 04 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74als1005 : default so14,dil14 {
	newattr "$comment" = "Buffered 05 (24mA IOL)" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74als1008 : default so14,dil14 {
	newattr "$comment" = "Buffered 08 (24mA IOL)" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als1010 : default so14,dil14 {
	newattr "$comment" = "Buffered 10 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74als1011 : default so14,dil14 {
	newattr "$comment" = "Buffered 11 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74als1020 : default so14,dil14 {
	newattr "$comment" = "Buffered 20 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74als1032 : default so14,dil14 {
	newattr "$comment" = "Buffered 32 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als1034 : default so14,dil14 {
	newattr "$comment" = "Buffered 34 (24mA IOL)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74als1035 : default so14,dil14 {
	newattr "$comment" = "Buffered 35 (24mA IOL)" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74als1036 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Positive NOR" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74als1240 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 240" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als1241 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 241" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als1242 : default dil14 {
	newattr "$comment" = "Reduced Power 242" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74als1243 : default so14,dil14 {
	newattr "$comment" = "Reduced Power 243" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74als1244 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 244" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als1245 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceivers" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1620 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceivers inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1621 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceivers noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1622 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceivers inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1623 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceivers noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1638 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 638" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1639 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 639" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1640 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 640" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1641 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 641" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1642 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 642" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1643 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 643" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1644 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 644" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1645 : default so20,dil20 {
	newattr "$comment" = "Reduced Power 645" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74als1804 : default dil20 {
	newattr "$comment" = "804 with Center Pinning" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (15) ;
	net "vcc" : (5) ;
	xlat ( a, b, y)
	  to ( 6, 7, 8)
	  or ( 9,10,11)
	  or (12,13,14)
	  or (17,18,16)
	  or (20, 1,19)
	  or ( 3, 4, 2) ;
	swap ( (( 6, 7), 8),
	       (( 9,10),11),
	       ((12,13),14),
	       ((17,18),16),
	       ((20, 1),19),
	       (( 3, 4), 2) ) ;
	}

part 74als1808 : default dil20 {
	newattr "$comment" = "808 with Center Pinning" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (15) ;
	net "vcc" : (5) ;
	xlat ( a, b, y)
	  to ( 6, 7, 8)
	  or ( 9,10,11)
	  or (12,13,14)
	  or (17,18,16)
	  or (20, 1,19)
	  or ( 3, 4, 2) ;
	swap ( (( 6, 7), 8),
	       (( 9,10),11),
	       ((12,13),14),
	       ((17,18),16),
	       ((20, 1),19),
	       (( 3, 4), 2) ) ;
	}

part 74als1832 : default dil20 {
	newattr "$comment" = "832 with Center Pinning" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (15) ;
	net "vcc" : (5) ;
	xlat ( a, b, y)
	  to ( 6, 7, 8)
	  or ( 9,10,11)
	  or (12,13,14)
	  or (17,18,16)
	  or (20, 1,19)
	  or ( 3, 4, 2) ;
	swap ( (( 6, 7), 8),
	       (( 9,10),11),
	       ((12,13),14),
	       ((17,18),16),
	       ((20, 1),19),
	       (( 3, 4), 2) ) ;
	}

part 74als2240 : default so20,dil20 {
	newattr "$comment" = "MOS Memory Driver type 240" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als2242 : default so14,dil14 {
	newattr "$comment" = "MOS Memory Driver type 242" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74als2244 : default so20,dil20 {
	newattr "$comment" = "MOS Memory Driver type 244" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74als2540 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer, Output Resistor inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74als2541 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer, Output Resistor noninv." ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 74als8003 : default so8,dil8 {
	newattr "$comment" = "Dual 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (4) ;
	net "vcc" : (8) ;
	xlat (a,b,y)
	  to (1,2,3)
	  or (6,7,5) ;
	swap ( (( 1, 2), 3), (( 6, 7), 5) ) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.