loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d54ls.def                                 */
/* SCM Library   : d54ls.ddb                                 */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - Bipolar TTL Low Power Schottky / Series 54LS            */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 54  = Military (-55..125 Degree Celcius)  */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 54ls00 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls01 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 54ls02 : default dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 54ls03 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls04 : default dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54ls05 : default dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54ls06 : default dil14 {
	newattr "$comment" = "Hex Inverter/Buffer, 30V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54ls07 : default dil14 {
	newattr "$comment" = "Hex Buffer, 30V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54ls08 : default dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls09 : default dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls10 : default dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 54ls11 : default dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 54ls12 : default dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 54ls13 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54ls14 : default dil14 {
	newattr "$comment" = "Hex Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54ls15 : default dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 54ls16 : default dil14 {
	newattr "$comment" = "Hex Inverter/Buffer, 15V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54ls17 : default dil14 {
	newattr "$comment" = "Hex Buffer, 15V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54ls18 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54ls19 : default dil14 {
	newattr "$comment" = "Hex Schmitt Trigger Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54ls20 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54ls21 : default dil14 {
	newattr "$comment" = "Dual 4 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54ls22 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54ls24 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls26 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND, 15V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls27 : default dil14 {
	newattr "$comment" = "Triple 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 54ls28 : default dil14 {
	newattr "$comment" = "Quad 2 Input NOR Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 54ls30 : default dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 54ls31 : mainpart dil16 {
	newattr "$comment" = "Delay Elements" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,y)
	  to ( 5, 6,7)
	  or (10,11,9) ;
	swap ( (( 5, 6), 7), ((10,11), 9) ) ;
	}

part 54ls31x : subpart 54ls31 {
	pin (a,y) ;
	xlat ( a, y)
	  to ( 3, 4)
	  or (13,12) ;
	swap ( ( 3, 4), (13,12) ) ;
	}

part 54ls31y : subpart 54ls31 {
	pin (a,y) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or (15,14) ;
	swap ( ( 1, 2), (15,14) ) ;
	}

part 54ls32 : default dil14 {
	newattr "$comment" = "Quad 2 Input OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls33 : default dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 54ls37 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls38 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls40 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54ls42 : default dil16 {
	newattr "$comment" = "BCD to Decimal Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 54ls47 : default dil16 {
	newattr "$comment" = "BCD to 7-Segment Decoder, 15V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 54ls48 : default dil16 {
	newattr "$comment" = "BCD to 7-Segment Decoder/Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 54ls49 : default dil14 {
	newattr "$comment" = "BCD to 7-Segment Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (bi,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (bi,a0,a1,a2,a3, a, b,c,d,e, f, g)
	  to ( 3, 5, 1, 2, 4,11,10,9,8,6,13,12) ;
	}

part 54ls51 : mainpart dil14 {
	newattr "$comment" = "3-3/2-2 Input AND-OR-Invert Gates" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c,d, e, f,y)
	  to (1,12,13,9,10,11,8) ;
	swap ( [  (( 1,12,13)), (( 9,10,11)), 8 ] ) ;
	}

part 54ls51x : subpart 54ls51 {
	pin (a,b,c,d,y) ;
	xlat (a,b,c,d,y)
	  to (2,3,4,5,6) ;
	swap ( [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 54ls54 : default dil14 {
	newattr "$comment" = "2-3-3-2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h, i, j,y)
	  to (1,2,3,4,5,9,10,11,12,13,6) ;
	swap internal ( (( 1, 2)), ((12,13)) ) ;
	swap internal ( (( 3, 4, 5)), (( 9,10,11)) ) ;
	}

part 54ls55 : default dil14 {
	newattr "$comment" = "2 Wide 4 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d, e, f, g, h,y)
	  to (1,2,3,4,10,11,12,13,8) ;
	swap internal ( (( 1, 2, 3, 4)), ((10,11,12,13)) ) ;
	}

part 54ls56 : default dil8 {
	newattr "$comment" = "Frequency Divider 50 to 1" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,clka,clkb,qa,qb,qc) ;
	net "vss" : (4) ;
	net "vcc" : (2) ;
	xlat (clr,clka,clkb,qa,qb,qc)
	  to (  6,   5,   1, 3, 7, 8) ;
	}

part 54ls57 : default dil8 {
	newattr "$comment" = "Frequency Divider 60 to 1" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,clka,clkb,qa,qb,qc) ;
	net "vss" : (4) ;
	net "vcc" : (2) ;
	xlat (clr,clka,clkb,qa,qb,qc)
	  to (  6,   5,   1, 3, 7, 8) ;
	}

part 54ls63 : default dil14 {
	newattr "$comment" = "Hex Current Sensing Interface Gate" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 4, 3)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (10,11)
	  or (13,12) ;
	swap ( ( 1, 2), ( 4, 3), ( 5, 6), ( 9, 8), (10,11), (13,12) ) ;
	}

part 54ls68 : default dil16 {
	newattr "$comment" = "Dual 40 MHz Decade Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (1clk1,1qa,/1clr,1clk2,1qb,1qc,1qd,/2clr,2clk,2qa,2qb,2qc,2qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (1clk1,1qa,/1clr,1clk2,1qb,1qc,1qd,/2clr,2clk,2qa,2qb,2qc,2qd)
	  to (    1, 14,    4,   15,  2, 13,  3,   11,   9,  7, 10,  5, 12) ;
	}

part 54ls69 : default dil16 {
	newattr "$comment" = "Dual 40 MHz 4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (1clk1,1qa,/1clr,1clk2,1qb,1qc,1qd,/2clr,2clk,2qa,2qb,2qc,2qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (1clk1,1qa,/1clr,1clk2,1qb,1qc,1qd,/2clr,2clk,2qa,2qb,2qc,2qd)
	  to (    1, 14,    4,   15,  2, 13,  3,   11,   9,  7, 10,  5, 12) ;
	}

part 54ls73 : default dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (j,clk,k,/clr,q,/q) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat ( j,clk, k,/clr, q,/q)
	  to (14,  1, 3,   2,12,13)
	  or ( 7,  5,10,   6, 9, 8) ;
	swap ( (14, 1, 3, 2,12,13), ( 7, 5,10, 6, 9, 8) ) ;
	}

part 54ls74 : default dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 54ls75 : default dil16 {
	newattr "$comment" = "Quad Bistable Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (d0,d1,c,q0,/q0,q1,/q1) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (d0,d1, c,q0,/q0,q1,/q1)
	  to ( 2, 3,13,16,  1,15, 14)
	  or ( 6, 7, 4,10, 11, 9,  8) ;
	swap ( ( 2, 3,13,16, 1,15,14), ( 6, 7, 4,10,11, 9, 8) ) ;
	}

part 54ls76 : default dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (j,k,clk,/pre,/clr,q,/q) ;
	net "vss" : (13) ;
	net "vcc" : (5) ;
	xlat (j, k,clk,/pre,/clr, q,/q)
	  to (4,16,  1,   2,   3,15,14)
	  or (9,12,  6,   7,   8,11,10) ;
	swap ( ( 4,16, 1, 2, 3,15,14), ( 9,12, 6, 7, 8,11,10) ) ;
	}

part 54ls77 : default dil14 {
	newattr "$comment" = "4 Bit Bistable Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (c,d0,d1,q0,q1) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat ( c,d0,d1,q0,q1)
	  to (12, 1, 2,14,13)
	  or ( 3, 5, 6, 9, 8) ;
	swap ( (12, 1,14, 2,13), ( 3, 5, 9, 6, 8) ) ;
	}

part 54ls78 : default dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Common Clear/Clock" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/clr,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat (clk,/clr,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (  1,   5,    2, 3,14,13, 12,    6,10, 7, 8,  9) ;
	swap internal ( ( 2, 3,14,13,12), ( 6,10, 7, 8, 9) ) ;
	}

part 54ls83 : default dil16 {
	newattr "$comment" = "4 Bit Binary Full Adder, Fast Carry" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,ci,y0,y1,y2,y3,co) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,ci,y0,y1,y2,y3,co)
	  to (10, 8, 3, 1,11, 7, 4,16,13, 9, 6, 2,15,14) ;
	swap internal ( (10, 8, 3, 1), (11, 7, 4,16) ) ;
	}

part 54ls85 : default dil16 {
	newattr "$comment" = "4 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q")
	  to (10,12,13,15, 9,11,14, 1,    2,    3,    4,    7,    6,    5) ;
	swap internal ( (10,12,13,15, 2, 7), ( 9,11,14, 1, 4, 5) ) ;
	}

part 54ls86 : default dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls90 : default dil14 {
	newattr "$comment" = "Decade Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,r91,r92,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02,r91,r92, a,qa,b,qb,qc,qd)
	  to (  2,  3,  6,  7,14,12,1, 9, 8,11) ;
	swap internal ( (( 2, 3)) ) ;
	swap internal ( (( 6, 7)) ) ;
	}

part 54ls91 : default dil14 {
	newattr "$comment" = "8 Bit Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (ck,a,b,q,/q) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (ck, a, b, q,/q)
	  to ( 9,12,11,13,14) ;
	swap internal ( ((12,11)) ) ;
	}

part 54ls92 : default dil14 {
	newattr "$comment" = "Divide by 12 Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02, a,qa,b,qb,qc,qd)
	  to (  6,  7,14,12,1,11, 9, 8) ;
	swap internal ( (( 6, 7)) ) ;
	}

part 54ls93 : default dil14 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02, a,qa,b,qb,qc,qd)
	  to (  2,  3,14,12,1, 9, 8,11) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 54ls95 : default dil14 {
	newattr "$comment" = "4 Bit Shift Register PISO" ;
	newattr "$ttlout" = "TP" ;
	pin (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd)
	  to (   6,   9,   8,  1,2,13,3,12,4,11,5,10) ;
	}

part 54ls96 : default dil16 {
	newattr "$comment" = "5 Bit Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,pre,ser,a,qa,b,qb,c,qc,d,qd,e,qe) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (/clr,clk,pre,ser,a,qa,b,qb,c,qc,d,qd,e,qe)
	  to (  16,  1,  8,  9,2,15,3,14,4,13,6,11,7,10) ;
	}

part 54ls107 : default dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (j,clk,k,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (j,clk, k,/clr,q,/q)
	  to (1, 12, 4,  13,3, 2)
	  or (8,  9,11,  10,5, 6) ;
	swap ( ( 1,12, 4,13, 3, 2), ( 8, 9,11,10, 5, 6) ) ;
	}

part 54ls109 : default dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,/k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk,/k,/clr, q,/q)
	  to (   5, 2,  4, 3,   1, 6, 7)
	  or (  11,14, 12,13,  15,10, 9) ;
	swap ( ( 5, 2, 4, 3, 1, 6, 7), (11,14,12,13,15,10, 9) ) ;
	}

part 54ls111 : default dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Data Lockout" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   2, 4,  5, 1,   3,7, 6)
	  or (  14,12, 11,15,  13,9,10) ;
	swap ( ( 2, 4, 5, 1, 3, 7, 6), (14,12,11,15,13, 9,10) ) ;
	}

part 54ls112 : default dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   4, 3,  1, 2,  15,5, 6)
	  or (  10,11, 13,12,  14,9, 7) ;
	swap ( ( 4, 3, 1, 2,15, 5, 6), (10,11,13,12,14, 9, 7) ) ;
	}

part 54ls113 : default dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre, j,clk, k,q,/q)
	  to (   4, 3,  1, 2,5, 6)
	  or (  10,11, 13,12,9, 8) ;
	swap ( ( 4, 3, 1, 2, 5, 6), (10,11,13,12, 9, 8) ) ;
	}

part 54ls114 : default dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (   1, 13,    4, 3, 2, 5,  6,   10,11,12, 9,  8) ;
	swap ( [  1,13, ( 4, 3, 2, 5, 6), (10,11,12, 9, 8) ] ) ;
	}

part 54ls122 : default dil14 {
	newattr "$comment" = "Monostable Multivibrator, Retriggerable" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,b1,b2,/clr,ri,cx,rxcx,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a1,a2,b1,b2,/clr,ri,cx,rxcx,q,/q)
	  to ( 1, 2, 3, 4,   5, 9,11,  13,8, 6) ;
	swap internal ( (( 1, 2)) ) ;
	swap internal ( (( 3, 4)) ) ;
	}

part 54ls123 : default dil16 {
	newattr "$comment" = "Dual Monostable Multivibrator, Retrigg." ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/clr,cx,rx,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,rx, q,/q)
	  to (1, 2,   3,14,15,13, 4)
	  or (9,10,  11, 6, 7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 54ls125 : default dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 54ls126 : default dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 54ls132 : default dil14 {
	newattr "$comment" = "Quad 2 Input Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls133 : default dil16 {
	newattr "$comment" = "13 Input Positive NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,k,l,m,y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,d,e,f,g, h, i, j, k, l, m,y)
	  to (1,2,3,4,5,6,7,10,11,12,13,14,15,9) ;
	swap ( (( 1, 2, 3, 4, 5, 6, 7,10,11,12,13,14,15), 9) ) ;
	}

part 54ls136 : default dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54ls137 : default dil16 {
	newattr "$comment" = "3 of 8 Decoder, Address Registers" ;
	newattr "$ttlout" = "TP" ;
	pin (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (  4,1,2,3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 54ls138 : default dil16 {
	newattr "$comment" = "3 of 8 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (1,2,3, 6,   4,   5,15,14,13,12,11,10, 9, 7) ;
	swap internal ( (( 4, 5)) ) ;
	}

part 54ls139 : default dil16 {
	newattr "$comment" = "Dual 2 of 4 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,/g,y0,y1,y2,y3)
	  to ( 2, 3, 1, 4, 5, 6, 7)
	  or (14,13,15,12,11,10, 9) ;
	swap ( ( 2, 3, 1, 4, 5, 6, 7), (14,13,15,12,11,10, 9) ) ;
	}

part 54ls145 : default dil16 {
	newattr "$comment" = "BCD to Decimal Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 54ls147 : default dil16 {
	newattr "$comment" = "10-Decimal to 4-BCD Priority Encoder" ;
	newattr "$ttlout" = "TP" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,i9,a,b,c,d) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,i9,a,b,c, d)
	  to (11,12,13, 1, 2, 3, 4, 5,10,9,7,6,14) ;
	}

part 54ls148 : default dil16 {
	newattr "$comment" = "8 to 3 Octal Priority Encoder" ;
	newattr "$ttlout" = "TP" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2)
	  to (10,11,12,13, 1, 2, 3, 4, 5,15,14, 9, 7, 6) ;
	}

part 54ls151 : default dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 54ls152 : default dil14 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	pin (d0,d1,d2,d3,d4,d5,d6,d7,a,b,c,w) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (d0,d1,d2,d3,d4,d5,d6,d7, a,b,c,w)
	  to ( 5, 4, 3, 2, 1,13,12,11,10,9,8,6) ;
	}

part 54ls153 : default dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 54ls154 : default dil24,dil24b {
	newattr "$comment" = "4 of 16 Line Decoder/Demultiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,
	     y14,y15) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat ( a, b, c, d,/g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,
	      y13,y14,y15)
	  to (23,22,21,20, 18, 19, 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 13, 14,
	       15, 16, 17) ;
	swap internal ( ((18,19)) ) ;
	}

part 54ls155 : default dil16 {
	newattr "$comment" = "Dual 1 of 4 Decoder/Demultiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3)
	  to (13, 3,  2, 1,  7,  6,  5,  4, 14, 15,  9, 10, 11, 12) ;
	}

part 54ls156 : default dil16 {
	newattr "$comment" = "Dual 1 of 4 Decoder/Demultiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3)
	  to (13, 3,  2, 1,  7,  6,  5,  4, 14, 15,  9, 10, 11, 12) ;
	}

part 54ls157 : default dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 54ls158 : default dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 54ls160 : default dil16 {
	newattr "$comment" = "BCD Decade Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 54ls161 : default dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 54ls162 : default dil16 {
	newattr "$comment" = "BCD Decade Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 54ls163 : default dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 54ls164 : default dil14 {
	newattr "$comment" = "8 Bit Shift Register SIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh)
	  to (   9,  8,1,2, 3, 4, 5, 6,10,11,12,13) ;
	swap internal ( (( 1, 2)) ) ;
	}

part 54ls165 : default dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh,/qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (shld,clkinh,clk,ser, a, b, c, d,e,f,g,h,qh,/qh)
	  to (   1,    15,  2, 10,11,12,13,14,3,4,5,6, 9,  7) ;
	}

part 54ls166 : default dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clkinh,clk,ser,a,b,c,d, e, f, g, h,qh)
	  to (   9,  15,     6,  7,  1,2,3,4,5,10,11,12,14,13) ;
	}

part 54ls168 : default dil16 {
	newattr "$comment" = "4 Bit Decade Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 54ls169 : default dil16 {
	newattr "$comment" = "4 Bit Binary Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 54ls170 : default dil16 {
	newattr "$comment" = "4 by 4 Register File" ;
	newattr "$ttlout" = "TP" ;
	pin (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to ( 5, 4,14,13, 12, 11,15,10, 1, 9, 2, 7, 3, 6) ;
	}

part 54ls171 : default dil16 {
	newattr "$comment" = "Quad D-Flip-Flop, Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (  13, 12,14,15,  1, 4, 3,  2, 5, 6,  7,11,10,  9) ;
	swap ( [ 13,12,
	       (14,15, 1),
	       ( 4, 3, 2),
	       ( 5, 6, 7),
	       (11,10, 9) ] ) ;
	}

part 54ls173 : default dil16 {
	newattr "$comment" = "Quad D Register" ;
	newattr "$ttlout" = "TS" ;
	pin (clr,m,n,/g1,/g2,clk,1d,1q,2d,2q,3d,3q,4d,4q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,m,n,/g1,/g2,clk,1d,1q,2d,2q,3d,3q,4d,4q)
	  to ( 15,1,2,  9, 10,  7,14, 3,13, 4,12, 5,11, 6) ;
	swap internal ( (( 1, 2)) ) ;
	swap internal ( (( 9,10)) ) ;
	}

part 54ls174 : default dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,d2,q2,d3,d4,q3,q4,d5,q5,d6,q6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,d2,q2,d3,q3,d4,q4,d5,q5,d6,q6)
	  to (   1,  9, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  1, 9,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 54ls175 : default dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (   1,  9, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  1, 9,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 54ls181 : default dil24,dil24b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to ( 6, 5, 4, 3,8, 7,15,17,   14,    16,  2,  1,  9, 23, 22, 10,
	       21, 20, 11, 19, 18, 13) ;
	}

part 54ls182 : default dil16 {
	newattr "$comment" = "16 Bit Look-Ahead Carry Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	     /g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,"cn+x","cn+y","cn+z",/p,
	      /g)
	  to ( 13,  4,  3,  2,  1, 15, 14,  6,  5,    12,    11,     9, 7,
	      10) ;
	}

part 54ls183 : default dil14 {
	newattr "$comment" = "Dual Carry Save Full Adder" ;
	newattr "$ttlout" = "TP" ;
	pin (ci,a,b,co,s) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (ci, a, b,co,s)
	  to ( 4, 1, 3, 5,6)
	  or (11,13,12,10,8) ;
	swap ( (( 1, 3), 4, 5, 6), ((13,12),11,10, 8) ) ;
	}

part 54ls189 : default dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3)
	  to ( 1,15,14,13,  2, 3, 4,  5, 6,  7,10,  9,12, 11) ;
	}

part 54ls190 : default dil16 {
	newattr "$comment" = "Synchronous Up/Down BCD Counter" ;
	newattr "$ttlout" = "OC" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 54ls191 : default dil16 {
	newattr "$comment" = "Synchronous Up/Down Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 54ls192 : default dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock BCD Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 54ls193 : default dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 54ls194 : default dil16 {
	newattr "$comment" = "4 Bit Universal Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd)
	  to (   1, 9,10, 11,    2,3,15,4,14,5,13,6,    7,12) ;
	}

part 54ls195 : default dil16 {
	newattr "$comment" = "4 Bit Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd)
	  to (   1,   9, 10,2, 3,4,15,5,14,6,13,7,12, 11) ;
	}

part 54ls196 : default dil14 {
	newattr "$comment" = "Presetable Decade (Bi-Quinary) Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/ld,/clr,clk1,a,qa,clk2,b,c,d,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/ld,/clr,clk1,a,qa,clk2, b,c, d,qb,qc,qd)
	  to (  1,  13,   8,4, 5,   6,10,3,11, 9, 2,12) ;
	}

part 54ls197 : default dil14 {
	newattr "$comment" = "Presetable 4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/ld,/clr,clk1,a,qa,clk2,b,c,d,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/ld,/clr,clk1,a,qa,clk2, b,c, d,qb,qc,qd)
	  to (  1,  13,   8,4, 5,   6,10,3,11, 9, 2,12) ;
	}

part 54ls219 : default dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,15,14,13,  2, 3, 4, 5, 6, 7,10, 9,12,11) ;
	}

part 54ls221 : default dil16 {
	newattr "$comment" = "Dual Monostable Multivibr., Schm.Trigger" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/clr,cx,"rx/cx",q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,"rx/cx", q,/q)
	  to (1, 2,   3,14,     15,13, 4)
	  or (9,10,  11, 6,      7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 54ls222 : default dil20 {
	newattr "$comment" = "Asynchronous FIFO Memory 16x4 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (oe,/clr,ldck,ire,unck,ore,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (oe,/clr,ldck,ire,unck,ore,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,  11,   4,  2,  19, 18, 3,  17, 5,16, 7,14, 8,13, 9,12) ;
	swap internal ( ( 5,16), ( 7,14), ( 8,13), ( 9,12) ) ;
	}

part 54ls224 : default dil16 {
	newattr "$comment" = "Asynchronous FIFO Memory 16x4 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (oe,/clr,ldck,unck,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (oe,/clr,ldck,unck,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,   9,   3,  15, 2,  14, 4,13, 5,12, 6,11, 7,10) ;
	swap internal ( ( 4,13), ( 5,12), ( 6,11), ( 7,10) ) ;
	}

part 54ls227 : default dil20 {
	newattr "$comment" = "Asynchronous FIFO Memory 16x4 Bit" ;
	newattr "$ttlout" = "OC" ;
	pin (oe,/clr,ldck,ire,unck,ore,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (oe,/clr,ldck,ire,unck,ore,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,  11,   4,  2,  19, 18, 3,  17, 5,16, 7,14, 8,13, 9,12) ;
	swap internal ( ( 5,16), ( 7,14), ( 8,13), ( 9,12) ) ;
	}

part 54ls228 : default dil16 {
	newattr "$comment" = "Asynchronous FIFO Memory 16x4 Bit" ;
	newattr "$ttlout" = "OC" ;
	pin (oe,/clr,ldck,unck,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (oe,/clr,ldck,unck,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,   9,   3,  15, 2,  14, 4,13, 5,12, 6,11, 7,10) ;
	swap internal ( ( 4,13), ( 5,12), ( 6,11), ( 7,10) ) ;
	}

part 54ls240 : default dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54ls241 : default dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54ls242 : default dil14 {
	newattr "$comment" = "Quad Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 54ls243 : default dil14 {
	newattr "$comment" = "Quad Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 54ls244 : default dil20 {
	newattr "$comment" = "Octal Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54ls245 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls246 : default dil16 {
	newattr "$comment" = "BCD to 7 Segment Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 54ls247 : default dil16 {
	newattr "$comment" = "BCD to 7 Segment Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 54ls248 : default dil16 {
	newattr "$comment" = "BCD to 7 Segment Decoder/Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 54ls249 : default dil16 {
	newattr "$comment" = "BCD to 7 Segment Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 54ls251 : default dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 54ls253 : default dil16 {
	newattr "$comment" = "Dual 4 to 1 Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 54ls257 : default dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 54ls258 : default dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 54ls259 : default dil16 {
	newattr "$comment" = "8 Bit Addressable Set-Reset Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,/g,d,/clr,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (s0,s1,s2,/g, d,/clr,q0,q1,q2,q3,q4,q5,q6,q7)
	  to ( 1, 2, 3,14,13,  15, 4, 5, 6, 7, 9,10,11,12) ;
	}

part 54ls260 : default dil14 {
	newattr "$comment" = "Dual 5 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c, d, e,y)
	  to (1,2,3,12,13,5)
	  or (4,8,9,10,11,6) ;
	swap ( (( 1, 2, 3,12,13), 5), (( 4, 8, 9,10,11), 6) ) ;
	}

part 54ls261 : default dil16 {
	newattr "$comment" = "4 by 2 Bit Parallel Binary Multiplier" ;
	newattr "$ttlout" = "TP" ;
	pin (b0,b1,b2,b3,b4,m0,m1,m2,g,q0,q1,q2,q3,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (b0,b1,b2,b3,b4,m0,m1,m2,g,q0,q1,q2,q3,/q4)
	  to (13,14,15, 1, 2,11,12, 4,3,10, 9, 7, 6,  5) ;
	}

part 54ls266 : default dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive NOR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((12,13),11) ) ;
	}

part 54ls273 : default dil20 {
	newattr "$comment" = "Octal D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (   1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 54ls280 : default dil14 {
	newattr "$comment" = "9 Bit Odd/Even Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,even,odd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,even,odd)
	  to (8,9,10,11,12,13,1,2,4,   5,  6) ;
	swap ( (( 8, 9,10,11,12,13, 1, 2, 4), 5, 6) ) ;
	}

part 54ls283 : default dil16 {
	newattr "$comment" = "4 Bit Full Adder, Fast Carry" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4)
	  to ( 5, 3,14,12, 6, 2,15,11, 7, 4, 1,13,10, 9) ;
	swap internal ( (( 5, 6),( 3, 2),(14,15),(12,11)) ) ;
	}

part 54ls289 : default dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,/q0,d1,/q1,d2,/q2,d3,/q3)
	  to ( 1,15,14,13,  2, 3, 4,  5, 6,  7,10,  9,12, 11) ;
	}

part 54ls290 : default dil14 {
	newattr "$comment" = "Decade Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,r91,r92,a,qa,b,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (r01,r02,r91,r92, a,qa, b,qb,qc,qd)
	  to ( 12, 13,  1,  3,10, 9,11, 5, 4, 8) ;
	swap internal ( ((12,13)) ) ;
	swap internal ( (( 1, 3)) ) ;
	}

part 54ls292 : default dil16 {
	newattr "$comment" = "30 Bit Programmable Frequency Divider" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk1,clk2,a,b,c,d,e,tp1,tp2,tp3,q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk1,clk2, a,b, c, d,e,tp1,tp2,tp3,q)
	  to (  11,   4,   5,10,1,15,14,2,  3,  6, 13,7) ;
	}

part 54ls293 : default dil14 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,a,qa,b,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (r01,r02, a,qa, b,qb,qc,qd)
	  to ( 12, 13,10, 9,11, 5, 4, 8) ;
	swap internal ( ((12,13)) ) ;
	}

part 54ls294 : default dil16 {
	newattr "$comment" = "4 Bit Binary Counter Frequency Divider" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk1,clk2,a,b,c,d,tp,q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk1,clk2,a,b, c, d,tp,q)
	  to (  11,   4,   5,2,1,15,14, 3,7) ;
	}

part 54ls295 : default dil14 {
	newattr "$comment" = "4 Bit Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd)
	  to ( 8,   6,  9,  1,2,13,3,12,4,11,5,10) ;
	}

part 54ls297 : default dil16 {
	newattr "$comment" = "Digital Phase Locked Loop" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,kclk,du,enctr,idclk,pa1,pb,pa2,idout,xorpd,ecpd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b, c, d,kclk,du,enctr,idclk,pa1,pb,pa2,idout,xorpd,ecpd)
	  to (2,1,15,14,   4, 6,    3,    5,  9,10, 13,    7,   11,  12) ;
	}

part 54ls298 : default dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer, Storage" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd)
	  to (10, 11, 3, 2,15, 4, 1,14, 9, 5,13, 7, 6,12) ;
	swap ( [ 10,11,
	       ( 3, 2,15),
	       ( 4, 1,14),
	       ( 9, 5,13),
	       ( 7, 6,12) ] ) ;
	}

part 54ls299 : default dil20 {
	newattr "$comment" = "8 Bit Universal PIPO Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 54ls319 : default dil16 {
	newattr "$comment" = "64 (16x4) Bit RAM noninv" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,a2,a3,/cs,rw,d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,/cs,rw,d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,15,14,13,  2, 3, 4, 5, 6, 7,10, 9,12,11) ;
	}

part 54ls320 : default dil16 {
	newattr "$comment" = "Crystal Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (tank1,tank2,xtal1,xtal2,"vcc'",ffd,f,/f,"f'","/f'",ffq) ;
	net "vss" : (3,8) ;
	net "vcc" : (16) ;
	xlat (tank1,tank2,xtal1,xtal2,"vcc'",ffd,f,/f,"f'","/f'",ffq)
	  to (    1,    2,   14,   15,    11,  5,7,12,  10,    9,  4) ;
	}

part 54ls321 : default dil16 {
	newattr "$comment" = "Crystal Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (tank1,tank2,xtal1,xtal2,"vcc'",ffd,f,/f,"f'","/f'","f/2","f/4",
	     ffq) ;
	net "vss" : (3,8) ;
	net "vcc" : (16) ;
	xlat (tank1,tank2,xtal1,xtal2,"vcc'",ffd,f,/f,"f'","/f'","f/2","f/4",
	      ffq)
	  to (    1,    2,   14,   15,    11,  5,7,12,  10,    9,   13,    6,
	        4) ;
	}

part 54ls322 : default dil20 {
	newattr "$comment" = "8 Bit Shift Register, Sign Extend" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/oe,/g,"s/p",clk,/se,ds,d0,d1,"a/qa","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh","qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/oe,/g,"s/p",clk,/se,ds,d0,d1,"a/qa","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh","qh'")
	  to (   9,  8, 1,    2, 11, 18,19, 3,17,     4,    16,     5,    15,
	           6,    14,     7,    13,   12) ;
	}

part 54ls323 : default dil20 {
	newattr "$comment" = "8 Bit Shift/Storage Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 54ls347 : default dil16 {
	newattr "$comment" = "LS47 with 7 Volt Output" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 54ls348 : default dil16 {
	newattr "$comment" = "8 to 3 Line Priority Encoder" ;
	newattr "$ttlout" = "TS" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2)
	  to (10,11,12,13, 1, 2, 3, 4, 5,15,14, 9, 7, 6) ;
	}

part 54ls352 : default dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 54ls353 : default dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 54ls354 : default dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 54ls355 : default dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 54ls356 : default dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 54ls357 : default dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 54ls365 : default dil16 {
	newattr "$comment" = "Hex Buffer W/Common Enable" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	swap internal ( (( 1,15)) ) ;
	}

part 54ls366 : default dil16 {
	newattr "$comment" = "Hex Inverter W/Common Enable" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6)
	  to (  1, 15, 2, 3, 4, 5, 6, 7,10, 9,12,11,14,13) ;
	swap internal ( ( 2, 3),
	                ( 4, 5),
	                ( 6, 7),
	                (10, 9),
	                (12,11),
	                (14,13) ) ;
	swap internal ( (( 1,15)) ) ;
	}

part 54ls367 : default dil16 {
	newattr "$comment" = "Hex Buffer 4 Bit and 2 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2,  3,  4,  5,  6,  7, 10,  9) ;
	xlat (/2g,2a1,2y1,2a2,2y2)
	  to ( 15, 12, 11, 14, 13) ;
	swap internal ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), (10, 9) ] ) ;
	swap internal ( [ 15, (12,11), (14,13) ] ) ;
	}

part 54ls368 : default dil16 {
	newattr "$comment" = "Hex Inverter 4 Bit and 2 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,/2g,2a1,2y1,2a2,2y2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2,  3,  4,  5,  6,  7, 10,  9) ;
	xlat (/2g,2a1,2y1,2a2,2y2)
	  to ( 15, 12, 11, 14, 13) ;
	swap internal ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), (10, 9) ] ) ;
	swap internal ( [ 15, (12,11), (14,13) ] ) ;
	}

part 54ls373 : default dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 54ls374 : default dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 54ls375 : default dil16 {
	newattr "$comment" = "Quad Bistable Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (1d,c,1q,/1q,2d,2q,/2q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( c,1d,1q,/1q,2d,2q,/2q)
	  to ( 4, 1, 3,  2, 7, 5,  6)
	  or (12, 9,11, 10,15,13, 14) ;
	swap ( [  4, ( 1, 3, 2), ( 7, 5, 6) ],
	       [ 12, ( 9,11,10), (15,13,14) ] ) ;
	}

part 54ls377 : default dil20 {
	newattr "$comment" = "Octal D-Flip-Flop with Data Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to ( 11, 1, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [ 11, 1,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 54ls378 : default dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q)
	  to (  9, 1, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  9, 1,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 54ls379 : default dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,/1q,2d,2q,/2q,3d,3q,/3q,4d,4q,/4q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,/g,1d,1q,/1q,2d,2q,/2q,3d,3q,/3q,4d,4q,/4q)
	  to (  9, 1, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  9, 1,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 54ls381 : default dil20 {
	newattr "$comment" = "ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,cn,/p,/g,a0,b0,f0,a1,b1,f1,a2,b2,f2,a3,b3,f3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,s2,cn,/p,/g,a0,b0,f0,a1,b1,f1,a2,b2,f2,a3,b3,f3)
	  to ( 5, 6, 7,15,14,13, 3, 4, 8, 1, 2, 9,19,18,11,17,16,12) ;
	}

part 54ls382 : default dil20 {
	newattr "$comment" = "4 Bit Arithemetic Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,cn,a0,b0,f0,a1,b1,f1,a2,b2,a3,b3,f2,ovr,"cn+4",f3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,s2,cn,a0,b0,f0,a1,b1,f1,a2,b2,a3,b3,f2,ovr,"cn+4",f3)
	  to ( 5, 6, 7,15, 3, 4, 8, 1, 2, 9,19,18,17,16,11, 13,    14,12) ;
	}

part 54ls384 : default dil16 {
	newattr "$comment" = "8 by 1 Bit Two's-Complement Multiplier" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,mode,clk,x0,x1,x2,x3,x4,x5,x6,x7,y,k,prod) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,mode,clk,x0,x1,x2,x3,x4,x5,x6,x7, y, k,prod)
	  to (   1,   9,  7, 5, 4, 3, 2,14,13,12,11,15,10,   6) ;
	}

part 54ls385 : default dil20 {
	newattr "$comment" = "Quad Serial Adder/Substractor" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,"1s/a",1a,1b,1s,"2s/a",2a,2b,2s,"3s/a",3a,3b,3s,"4s/a",
	     4a,4b,4s) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,clk,"1s/a",1a,1b,1s,"2s/a",2a,2b,2s,"3s/a",3a,3b,3s,"4s/a",
	      4a,4b,4s)
	  to (  11,  1,     3, 5, 4, 2,     8, 6, 7, 9,    13,15,14,12,    18,
	      16,17,19) ;
	swap ( [ 11, 1,
	       ( 3, 5, 4, 2),
	       ( 8, 6, 7, 9),
	       (13,15,14,12),
	       (18,16,17,19) ] ) ;
	}

part 54ls386 : default dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((12,13),11) ) ;
	}

part 54ls390 : default dil16 {
	newattr "$comment" = "Dual 4 Bit Decade and Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,a,qa,b,qb,qc,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr, a,qa, b,qb,qc,qd)
	  to (   2, 1, 3, 4, 5, 6, 7)
	  or (  14,15,13,12,11,10, 9) ;
	swap ( [  2, 1, 3, 4, 5, 6, 7 ],
	       [ 14,15,13,12,11,10, 9 ] ) ;
	}

part 54ls393 : default dil14 {
	newattr "$comment" = "Dual 4 Bit Decade and Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,a,qa,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (clr, a,qa,qb,qc,qd)
	  to (  2, 1, 3, 4, 5, 6)
	  or ( 12,13,11,10, 9, 8) ;
	swap ( ( 2, 1, 3, 4, 5, 6), (12,13,11,10, 9, 8) ) ;
	}

part 54ls395 : default dil16 {
	newattr "$comment" = "4 Bit Cascadable Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd,"qd'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd,"qd'")
	  to (   1,  9,   7, 10,  2,3,15,4,14,5,13,6,12,   11) ;
	}

part 54ls396 : default dil16 {
	newattr "$comment" = "Octal Storage Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,clk,d1,1q1,2q1,d2,1q2,2q2,d3,1q3,2q3,d4,1q4,2q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,clk,d1,1q1,2q1,d2,1q2,2q2,d3,1q3,2q3,d4,1q4,2q4)
	  to (15,  7, 3,  2,  1, 6,  5,  4, 9, 10, 11,12, 13, 14) ;
	swap ( [ 15, 7,
	       ( 3, 2, 1),
	       ( 6, 5, 4),
	       ( 9,10,11),
	       (12,13,14) ] ) ;
	}

part 54ls398 : default dil20 {
	newattr "$comment" = "Quad 2 Input Multiplexer, Storage" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,ck,a1,a2,qa,/qa,b1,b2,qb,/qb,c1,c2,qc,/qc,d1,d2,qd,/qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (ws,ck,a1,a2,qa,/qa,b1,b2,qb,/qb,c1,c2,qc,/qc,d1,d2,qd,/qd)
	  to ( 1,11, 4, 5, 2,  3, 7, 6, 9,  8,14,15,12, 13,17,16,19, 18) ;
	swap ( [  1,11,
	       ( 4, 5, 2, 3),
	       ( 7, 6, 9, 8),
	       (14,15,12,13),
	       (17,16,19,18) ] ) ;
	}

part 54ls399 : default dil16 {
	newattr "$comment" = "Quad 2 Input MUX, Storage (25LS09)" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,ck,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ws,ck,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd)
	  to ( 1, 9, 3, 4, 2, 6, 5, 7,11,12,10,14,13,15) ;
	swap ( [  1, 9,
	       ( 3, 4, 2),
	       ( 6, 5, 7),
	       (11,12,10),
	       (14,13,15) ] ) ;
	}

part 54ls422 : default dil14 {
	newattr "$comment" = "Multivibrator (no Trigger from Clear)" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,b1,b2,/clr,ri,cx,rxcx,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a1,a2,b1,b2,/clr,ri,cx,rxcx,q,/q)
	  to ( 1, 2, 3, 4,   5, 9,11,  13,8, 6) ;
	swap internal ( (( 1, 2)) ) ;
	swap internal ( (( 3, 4)) ) ;
	}

part 54ls423 : default dil16 {
	newattr "$comment" = "Multivibrator (no Trigger from Clear)" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/clr,cx,rx,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,rx, q,/q)
	  to (1, 2,   3,14,15,13, 4)
	  or (9,10,  11, 6, 7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 54ls440 : default dil20 {
	newattr "$comment" = "Quad Tridirectional Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4)
	  to (11,12,  1, 17, 18, 19,16, 2, 3,15, 5, 4,14, 6, 7,13, 9, 8) ;
	swap ( [ 11,12, 1,17,18,19,
	       (16, 2, 3),
	       (15, 5, 4),
	       (14, 6, 7),
	       (13, 9, 8) ] ) ;
	}

part 54ls441 : default dil20 {
	newattr "$comment" = "Quad Tridirectional Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4)
	  to (11,12,  1, 17, 18, 19,16, 2, 3,15, 5, 4,14, 6, 7,13, 9, 8) ;
	swap ( [ 11,12, 1,17,18,19,
	       (16, 2, 3),
	       (15, 5, 4),
	       (14, 6, 7),
	       (13, 9, 8) ] ) ;
	}

part 54ls442 : default dil20 {
	newattr "$comment" = "Quad Tridirectional Bus Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4)
	  to (11,12,  1, 17, 18, 19,16, 2, 3,15, 5, 4,14, 6, 7,13, 9, 8) ;
	swap ( [ 11,12, 1,17,18,19,
	       (16, 2, 3),
	       (15, 5, 4),
	       (14, 6, 7),
	       (13, 9, 8) ] ) ;
	}

part 54ls443 : default dil20 {
	newattr "$comment" = "Quad Tridirectional Bus Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4)
	  to (11,12,  1, 17, 18, 19,16, 2, 3,15, 5, 4,14, 6, 7,13, 9, 8) ;
	swap ( [ 11,12, 1,17,18,19,
	       (16, 2, 3),
	       (15, 5, 4),
	       (14, 6, 7),
	       (13, 9, 8) ] ) ;
	}

part 54ls444 : default dil20 {
	newattr "$comment" = "Quad Tridirectional Bus Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4)
	  to (11,12,  1, 17, 18, 19,16, 2, 3,15, 5, 4,14, 6, 7,13, 9, 8) ;
	swap ( [ 11,12, 1,17,18,19,
	       (16, 2, 3),
	       (15, 5, 4),
	       (14, 6, 7),
	       (13, 9, 8) ] ) ;
	}

part 54ls445 : default dil16 {
	newattr "$comment" = "BCD to Decimal Decoder/Driver, 7V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 54ls446 : default dil16 {
	newattr "$comment" = "Quad Bus Transceivers" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,/gab,dir1,dir2,dir3,dir4,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/gba,/gab,dir1,dir2,dir3,dir4,a1,b1,a2,b2,a3,b3,a4,b4)
	  to (   1,  15,  13,   3,   6,  10, 2,14, 4,12, 5,11, 7, 9) ;
	swap ( [  1,15,13, 3, 6,10,
	       ( 2,14),
	       ( 4,12),
	       ( 5,11),
	       ( 7, 9) ] ) ;
	}

part 54ls447 : default dil16 {
	newattr "$comment" = "BCD to 7-Segment Decoder/Driver, 7V O/P" ;
	pin (/lt,bo,bi,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/lt,bo,bi,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to (  3, 4, 5, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 54ls448 : default dil20 {
	newattr "$comment" = "Quad Tridirectional Bus Transceiver" ;
	pin (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,/cs,/ga,/gb,/gc,a1,b1,c1,a2,b2,c2,a3,b3,c3,a4,b4,c4)
	  to (11,12,  1, 17, 18, 19,16, 2, 3,15, 5, 4,14, 6, 7,13, 9, 8) ;
	swap ( [ 11,12, 1,17,18,19,
	       (16, 2, 3),
	       (15, 5, 4),
	       (14, 6, 7),
	       (13, 9, 8) ] ) ;
	}

part 54ls449 : default dil16 {
	newattr "$comment" = "Quad Bus Transceivers" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,/gab,dir1,dir2,dir3,dir4,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/gba,/gab,dir1,dir2,dir3,dir4,a1,b1,a2,b2,a3,b3,a4,b4)
	  to (   1,  15,  13,   3,   6,  10, 2,14, 4,12, 5,11, 7, 9) ;
	swap ( [  1,15,13, 3, 6,10,
	       ( 2,14),
	       ( 4,12),
	       ( 5,11),
	       ( 7, 9) ] ) ;
	}

part 54ls465 : default dil20 {
	newattr "$comment" = "Octal Buffer Gate Enabled noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2, 3, 4, 5, 6, 7, 8, 9,12,11,14,13,16,15,18,17) ;
	swap ( [  1,19,
	       ( 2, 3),
	       ( 4, 5),
	       ( 6, 7),
	       ( 8, 9),
	       (12,11),
	       (14,13),
	       (16,15),
	       (18,17) ] ) ;
	}

part 54ls466 : default dil20 {
	newattr "$comment" = "Octal Buffer Gate Enabled inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2, 3, 4, 5, 6, 7, 8, 9,12,11,14,13,16,15,18,17) ;
	swap ( [  1,19,
	       ( 2, 3),
	       ( 4, 5),
	       ( 6, 7),
	       ( 8, 9),
	       (12,11),
	       (14,13),
	       (16,15),
	       (18,17) ] ) ;
	}

part 54ls467 : default dil20 {
	newattr "$comment" = "Octal Buffer Gated Enable noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2, 3, 4, 5, 6, 7, 8, 9)
	  or (19,12,11,14,13,16,15,18,17) ;
	swap ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), ( 8, 9) ],
	       [ 19, (12,11), (14,13), (16,15), (18,17) ] ) ;
	}

part 54ls468 : default dil20 {
	newattr "$comment" = "Octal Buffer Gated Enable inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2, 3, 4, 5, 6, 7, 8, 9)
	  or (19,12,11,14,13,16,15,18,17) ;
	swap ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), ( 8, 9) ],
	       [ 19, (12,11), (14,13), (16,15), (18,17) ] ) ;
	}

part 54ls490 : default dil16 {
	newattr "$comment" = "Dual 4 Bit Decade Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,set,/clk,qa,qb,qc,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,set,/clk,qa,qb,qc,qd)
	  to (  2,  4,   1, 3, 5, 6, 7)
	  or ( 14, 12,  15,13,11,10, 9) ;
	swap ( [  2, 4, 1, 3, 5, 6, 7 ],
	       [ 14,12,15,13,11,10, 9 ] ) ;
	}

part 54ls540 : default dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 54ls541 : default dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 54ls568 : default dil20 {
	newattr "$comment" = "4 Bit Decade Counter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (17,    1,  2,  12,   7,    9,   11,    8,  18,  19,3,16,4,15,
	      5,14,6,13) ;
	}

part 54ls569 : default dil20 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (17,    1,  2,  12,   7,    9,   11,    8,  18,  19,3,16,4,15,
	      5,14,6,13) ;
	}

part 54ls589 : default dil16 {
	newattr "$comment" = "8 Bit Shift Register In Latch/Serial Out" ;
	newattr "$ttlout" = "TS" ;
	pin ("sh/ld",sck,/oe,rck,ser,a,b,c,d,e,f,g,h,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ("sh/ld",sck,/oe,rck,ser, a,b,c,d,e,f,g,h,"qh'")
	  to (     13, 11, 10, 12, 14,15,1,2,3,4,5,6,7,    9) ;
	}

part 54ls590 : default dil16 {
	newattr "$comment" = "8 Bit Binary Counter, Output Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,rck,/ccken,cck,/cclr,/rco,qa,qb,qc,qd,qe,qf,qg,qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,rck,/ccken,cck,/cclr,/rco,qa,qb,qc,qd,qe,qf,qg,qh)
	  to (14, 13,    12, 11,   10,   9,15, 1, 2, 3, 4, 5, 6, 7) ;
	}

part 54ls591 : default dil16 {
	newattr "$comment" = "8 Bit Binary Counter, Output Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,rck,/ccken,cck,/cclr,/rco,qa,qb,qc,qd,qe,qf,qg,qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,rck,/ccken,cck,/cclr,/rco,qa,qb,qc,qd,qe,qf,qg,qh)
	  to (14, 13,    12, 11,   10,   9,15, 1, 2, 3, 4, 5, 6, 7) ;
	}

part 54ls592 : default dil16 {
	newattr "$comment" = "8 Bit Binary Counter, Input Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/cclr,/ccken,cck,/cload,rck,/rco,a,b,c,d,e,f,g,h) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cclr,/ccken,cck,/cload,rck,/rco, a,b,c,d,e,f,g,h)
	  to (   10,    12, 11,    14, 13,   9,15,1,2,3,4,5,6,7) ;
	}

part 54ls593 : default dil20 {
	newattr "$comment" = "8 Bit Binary Counter, I/O Register" ;
	newattr "$ttlout" = "TP" ;
	pin (g,/g,/cclr,ccken,/ccken,cck,/cload,/rcken,rck,/rco,"a/qa","b/qb",
	     "c/qc","d/qd","e/qe","f/qf","g/qg","h/qh") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat ( g,/g,/cclr,ccken,/ccken,cck,/cload,/rcken,rck,/rco,"a/qa",
	      "b/qb","c/qc","d/qd","e/qe","f/qf","g/qg","h/qh")
	  to (19,18,   12,   15,    14, 13,     9,    17, 16,  11,     1,
	           2,     3,     4,     5,     6,     7,     8) ;
	}

part 54ls594 : default dil16 {
	newattr "$comment" = "8 Bit Shift Register, Output Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/rclr,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/rclr,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'")
	  to (   13, 12,   10, 11, 14,15, 1, 2, 3, 4, 5, 6, 7,    9) ;
	}

part 54ls595 : default dil16 {
	newattr "$comment" = "8 Bit Shift Register, Output Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'")
	  to (13, 12,   10, 11, 14,15, 1, 2, 3, 4, 5, 6, 7,    9) ;
	}

part 54ls596 : default dil16 {
	newattr "$comment" = "8 Bit Shift Register, Output Register" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'")
	  to (13, 12,   10, 11, 14,15, 1, 2, 3, 4, 5, 6, 7,    9) ;
	}

part 54ls597 : default dil16 {
	newattr "$comment" = "8 Bit Shift Register, Input Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/sclr,sck,/sload,rck,ser,a,b,c,d,e,f,g,h,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/sclr,sck,/sload,rck,ser, a,b,c,d,e,f,g,h,"qh'")
	  to (   10, 11,    13, 12, 14,15,1,2,3,4,5,6,7,    9) ;
	}

part 54ls598 : default dil20 {
	newattr "$comment" = "8 Bit Shift Register, I/O Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,/sclr,/scken,sck,/sload,rck,ds,ser0,ser1,"a/qa","b/qb","c/qc",
	     "d/qe","e/qe","f/qf","g/qg","h/qh","qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,/sclr,/scken,sck,/sload,rck,ds,ser0,ser1,"a/qa","b/qb","c/qc",
	      "d/qe","e/qe","f/qf","g/qg","h/qh","qh'")
	  to (16,   12,    14, 13,     9, 15,19,  17,  18,     1,     2,     3,
	           4,     5,     6,     7,     8,   11) ;
	}

part 54ls599 : default dil16 {
	newattr "$comment" = "8 Bit Shift Register, Output Register" ;
	newattr "$ttlout" = "OC" ;
	pin (/rclr,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/rclr,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'")
	  to (   13, 12,   10, 11, 14,15, 1, 2, 3, 4, 5, 6, 7,    9) ;
	}

part 54ls604 : default dil28b {
	newattr "$comment" = "Octal 2 Input Multiplexed Register" ;
	newattr "$ttlout" = "TS" ;
	pin ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	     y6,a7,b7,y7,a8,b8,y8) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	      y6,a7,b7,y7,a8,b8,y8)
	  to (    2,  1, 3, 4,15, 5, 6,13, 7, 8,12, 9,10,11,27,26,16,25,24,
	      17,23,22,18,21,20,19) ;
	swap ( [  2, 1,
	       ( 3, 4,15),
	       ( 5, 6,13),
	       ( 7, 8,12),
	       ( 9,10,11),
	       (27,26,16),
	       (25,24,17),
	       (23,22,18),
	       (21,20,19) ] ) ;
	}

part 54ls605 : default dil28b {
	newattr "$comment" = "Octal 2 Input Multiplexed Register" ;
	newattr "$ttlout" = "OC" ;
	pin ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	     y6,a7,b7,y7,a8,b8,y8) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	      y6,a7,b7,y7,a8,b8,y8)
	  to (    2,  1, 3, 4,15, 5, 6,13, 7, 8,12, 9,10,11,27,26,16,25,24,
	      17,23,22,18,21,20,19) ;
	swap ( [  2, 1,
	       ( 3, 4,15),
	       ( 5, 6,13),
	       ( 7, 8,12),
	       ( 9,10,11),
	       (27,26,16),
	       (25,24,17),
	       (23,22,18),
	       (21,20,19) ] ) ;
	}

part 54ls606 : default dil28b {
	newattr "$comment" = "Octal 2 Input Multiplexed Register" ;
	newattr "$ttlout" = "TS" ;
	pin ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	     y6,a7,b7,y7,a8,b8,y8) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	      y6,a7,b7,y7,a8,b8,y8)
	  to (    2,  1, 3, 4,15, 5, 6,13, 7, 8,12, 9,10,11,27,26,16,25,24,
	      17,23,22,18,21,20,19) ;
	swap ( [  2, 1,
	       ( 3, 4,15),
	       ( 5, 6,13),
	       ( 7, 8,12),
	       ( 9,10,11),
	       (27,26,16),
	       (25,24,17),
	       (23,22,18),
	       (21,20,19) ] ) ;
	}

part 54ls607 : default dil28b {
	newattr "$comment" = "Octal 2 Input Multiplexed Register" ;
	newattr "$ttlout" = "OC" ;
	pin ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	     y6,a7,b7,y7,a8,b8,y8) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat ("a/b",clk,a1,b1,y1,a2,b2,y2,a3,b3,y3,a4,b4,y4,a5,b5,y5,a6,b6,
	      y6,a7,b7,y7,a8,b8,y8)
	  to (    2,  1, 3, 4,15, 5, 6,13, 7, 8,12, 9,10,11,27,26,16,25,24,
	      17,23,22,18,21,20,19) ;
	swap ( [  2, 1,
	       ( 3, 4,15),
	       ( 5, 6,13),
	       ( 7, 8,12),
	       ( 9,10,11),
	       (27,26,16),
	       (25,24,17),
	       (23,22,18),
	       (21,20,19) ] ) ;
	}

part 54ls610 : default dil40 {
	newattr "$comment" = "Memory Mapper, Output Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/cs,/me,c,/mm,"r/w",rs0,rs1,rs2,rs3,/stb,ma0,ma1,ma2,ma3,mo0,
	     mo1,mo2,mo3,mo4,mo5,mo6,mo7,mo8,mo9,mo10,mo11,d0,d1,d2,d3,d4,
	     d5,d6,d7,d8,d9,d10,d11) ;
	net "vss" : (20) ;
	net "vcc" : (40) ;
	xlat (/cs,/me, c,/mm,"r/w",rs0,rs1,rs2,rs3,/stb,ma0,ma1,ma2,ma3,mo0,
	      mo1,mo2,mo3,mo4,mo5,mo6,mo7,mo8,mo9,mo10,mo11,d0,d1,d2,d3,d4,
	      d5,d6,d7,d8,d9,d10,d11)
	  to (  4, 21,28, 13,    6, 36, 38,  1,  3,   5, 35, 37, 39,  2, 14,
	       15, 16, 17, 18, 19, 22, 23, 24, 25,  26,  27, 7, 8, 9,10,11,
	      12,29,30,31,32, 33, 34) ;
	}

part 54ls611 : default dil40 {
	newattr "$comment" = "Memory Mapper, Output Latch" ;
	newattr "$ttlout" = "OC" ;
	pin (/cs,/me,c,/mm,"r/w",rs0,rs1,rs2,rs3,/stb,ma0,ma1,ma2,ma3,mo0,
	     mo1,mo2,mo3,mo4,mo5,mo6,mo7,mo8,mo9,mo10,mo11,d0,d1,d2,d3,d4,
	     d5,d6,d7,d8,d9,d10,d11) ;
	net "vss" : (20) ;
	net "vcc" : (40) ;
	xlat (/cs,/me, c,/mm,"r/w",rs0,rs1,rs2,rs3,/stb,ma0,ma1,ma2,ma3,mo0,
	      mo1,mo2,mo3,mo4,mo5,mo6,mo7,mo8,mo9,mo10,mo11,d0,d1,d2,d3,d4,
	      d5,d6,d7,d8,d9,d10,d11)
	  to (  4, 21,28, 13,    6, 36, 38,  1,  3,   5, 35, 37, 39,  2, 14,
	       15, 16, 17, 18, 19, 22, 23, 24, 25,  26,  27, 7, 8, 9,10,11,
	      12,29,30,31,32, 33, 34) ;
	}

part 54ls612 : default dil40 {
	newattr "$comment" = "Memory Mapper, Output Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/cs,/me,/mm,"r/w",rs0,rs1,rs2,rs3,/stb,ma0,ma1,ma2,ma3,mo0,mo1,
	     mo2,mo3,mo4,mo5,mo6,mo7,mo8,mo9,mo10,mo11,d0,d1,d2,d3,d4,d5,
	     d6,d7,d8,d9,d10,d11) ;
	net "vss" : (20) ;
	net "vcc" : (40) ;
	xlat (/cs,/me,/mm,"r/w",rs0,rs1,rs2,rs3,/stb,ma0,ma1,ma2,ma3,mo0,
	      mo1,mo2,mo3,mo4,mo5,mo6,mo7,mo8,mo9,mo10,mo11,d0,d1,d2,d3,d4,
	      d5,d6,d7,d8,d9,d10,d11)
	  to (  4, 21, 13,    6, 36, 38,  1,  3,   5, 35, 37, 39,  2, 14,
	       15, 16, 17, 18, 19, 22, 23, 24, 25,  26,  27, 7, 8, 9,10,11,
	      12,29,30,31,32, 33, 34) ;
	}

part 54ls613 : default dil40 {
	newattr "$comment" = "Memory Mapper, Output Latch" ;
	newattr "$ttlout" = "OC" ;
	pin (/cs,/me,/mm,"r/w",rs0,rs1,rs2,rs3,/stb,ma0,ma1,ma2,ma3,mo0,mo1,
	     mo2,mo3,mo4,mo5,mo6,mo7,mo8,mo9,mo10,mo11,d0,d1,d2,d3,d4,d5,
	     d6,d7,d8,d9,d10,d11) ;
	net "vss" : (20) ;
	net "vcc" : (40) ;
	xlat (/cs,/me,/mm,"r/w",rs0,rs1,rs2,rs3,/stb,ma0,ma1,ma2,ma3,mo0,
	      mo1,mo2,mo3,mo4,mo5,mo6,mo7,mo8,mo9,mo10,mo11,d0,d1,d2,d3,d4,
	      d5,d6,d7,d8,d9,d10,d11)
	  to (  4, 21, 13,    6, 36, 38,  1,  3,   5, 35, 37, 39,  2, 14,
	       15, 16, 17, 18, 19, 22, 23, 24, 25,  26,  27, 7, 8, 9,10,11,
	      12,29,30,31,32, 33, 34) ;
	}

part 54ls620 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls621 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls622 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls623 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls624 : default dil14 {
	newattr "$comment" = "Voltage Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (oscvcc,oscgnd,/en,rng,fc,cx1,cx2,y,z) ;
	net "vss" : (7) ;
	net "vcc" : (9) ;
	xlat (oscvcc,oscgnd,/en,rng,fc,cx1,cx2,y,z)
	  to (    14,     1,  5,  2,13,  3,  4,6,8) ;
	}

part 54ls625 : default dil16 {
	newattr "$comment" = "Voltage Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (oscvcc,oscgnd,fc,cx1,cx2,y,z) ;
	net "vss" : (1) ;
	net "vcc" : (16) ;
	xlat (oscvcc,oscgnd,fc,cx1,cx2, y, z)
	  to (     7,     8, 6,  4,  5, 3, 2)
	  or (    10,     9,11, 13, 12,14,15) ;
	swap ( ( 7, 8, 6, 4, 5, 3, 2), (10, 9,11,13,12,14,15) ) ;
	}

part 54ls626 : default dil16 {
	newattr "$comment" = "Voltage Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (oscvcc,oscgnd,/1en,1fc,1cx1,1cx2,1y,1z,/2en,2fc,2cx1,2cx2,2y,
	     2z) ;
	net "vss" : (1) ;
	net "vcc" : (16) ;
	xlat (oscvcc,oscgnd,/1en,1fc,1cx1,1cx2,1y,1z,/2en,2fc,2cx1,2cx2,2y,
	      2z)
	  to (     7,     8,   4,  9,   5,   6, 3, 2,  13, 10,  12,  11,14,
	      15) ;
	swap ( [  7, 8, ( 4, 9, 5, 6, 3, 2), (13,10,12,11,14,15) ] ) ;
	}

part 54ls627 : default dil14 {
	newattr "$comment" = "Voltage Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (oscvcc,oscgnd,fc,cx1,cx2,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (oscvcc,oscgnd,fc,cx1,cx2,y)
	  to (     1,     5, 2,  3,  4,6)
	  or (    13,     9,12, 11, 10,8) ;
	swap ( ( 1, 5, 2, 3, 4, 6), (13, 9,12,11,10, 8) ) ;
	}

part 54ls628 : default dil14 {
	newattr "$comment" = "Voltage Controlled Osci (Temp.comp 624)" ;
	newattr "$ttlout" = "TP" ;
	pin (oscvcc,oscgnd,/en,rng,fc,cx1,cx2,rx1,rx2,y,z) ;
	net "vss" : (7) ;
	net "vcc" : (9) ;
	xlat (oscvcc,oscgnd,/en,rng,fc,cx1,cx2,rx1,rx2,y,z)
	  to (    14,     1,  5,  2,13,  3,  4, 11, 12,6,8) ;
	}

part 54ls629 : default dil16 {
	newattr "$comment" = "Voltage Controlled Osci (improved 124)" ;
	newattr "$ttlout" = "TP" ;
	pin (oscvcc,oscgnd,/1en,1rng,1fc,1cx1,1cx2,1y,/2en,2rng,2fc,2cx1,
	     2cx2,2y) ;
	net "vss" : (9) ;
	net "vcc" : (16) ;
	xlat (oscvcc,oscgnd,/1en,1rng,1fc,1cx1,1cx2,1y,/2en,2rng,2fc,2cx1,
	      2cx2,2y)
	  to (    15,     8,   6,   3,  2,   4,   5, 7,  11,  14,  1,  13,
	        12,10) ;
	swap ( [ 15, 8, ( 6, 3, 2, 4, 5, 7), (11,14, 1,13,12,10) ] ) ;
	}

part 54ls630 : default dil28b {
	newattr "$comment" = "16 Bit Error Detect/Correct" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,sef,def,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,db11,
	     db12,db13,db14,db15,cb0,cb1,cb2,cb3,cb4,cb5) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat (s0,s1,sef,def,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	      db11,db12,db13,db14,db15,cb0,cb1,cb2,cb3,cb4,cb5)
	  to (25,26, 27,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11,  12,
	        13,  15,  16,  17,  18, 24, 23, 22, 21, 20, 19) ;
	}

part 54ls631 : default dil28b {
	newattr "$comment" = "16 Bit Error Detect/Correct" ;
	newattr "$ttlout" = "OC" ;
	pin (s0,s1,sef,def,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,db11,
	     db12,db13,db14,db15,cb0,cb1,cb2,cb3,cb4,cb5) ;
	net "vss" : (14) ;
	net "vcc" : (28) ;
	xlat (s0,s1,sef,def,db0,db1,db2,db3,db4,db5,db6,db7,db8,db9,db10,
	      db11,db12,db13,db14,db15,cb0,cb1,cb2,cb3,cb4,cb5)
	  to (25,26, 27,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11,  12,
	        13,  15,  16,  17,  18, 24, 23, 22, 21, 20, 19) ;
	}

part 54ls636 : default dil20 {
	newattr "$comment" = "8 Bit Error Detect/Correct" ;
	newattr "$ttlout" = "TS" ;
	pin (s0,s1,sef,def,db0,db1,db2,db3,db4,db5,db6,db7,cb0,cb1,cb2,cb3,
	     cb4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,sef,def,db0,db1,db2,db3,db4,db5,db6,db7,cb0,cb1,cb2,cb3,
	      cb4)
	  to (17,18, 19,  1,  2,  3,  4,  5,  6,  7,  8,  9, 16, 15, 14, 13,
	       11) ;
	}

part 54ls637 : default dil20 {
	newattr "$comment" = "8 Bit Error Detect/Correct" ;
	newattr "$ttlout" = "OC" ;
	pin (s0,s1,sef,def,db0,db1,db2,db3,db4,db5,db6,db7,cb0,cb1,cb2,cb3,
	     cb4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,sef,def,db0,db1,db2,db3,db4,db5,db6,db7,cb0,cb1,cb2,cb3,
	      cb4)
	  to (17,18, 19,  1,  2,  3,  4,  5,  6,  7,  8,  9, 16, 15, 14, 13,
	       11) ;
	}

part 54ls638 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls639 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls640 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls641 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls642 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls643 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver true inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls644 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls645 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54ls646 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54ls647 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54ls648 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54ls649 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54ls651 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54ls652 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54ls653 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54ls654 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54ls668 : default dil16 {
	newattr "$comment" = "Synchronous 4 Bit Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 54ls669 : default dil16 {
	newattr "$comment" = "Synchronous 4 Bit Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 54ls670 : default dil16 {
	newattr "$comment" = "4 by 4 Register File" ;
	newattr "$ttlout" = "TS" ;
	pin (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to ( 5, 4,14,13, 12, 11,15,10, 1, 9, 2, 7, 3, 6) ;
	}

part 54ls671 : default dil20 {
	newattr "$comment" = "4 Bit Univ. Shift Register/Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/s",rck,/sclr,s0,s1,sck,casc,srser,a,qa,b,qb,c,qc,d,slser,
	     qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/s",rck,/sclr,s0,s1,sck,casc,srser,a,qa,b,qb,c,qc,d,slser,
	      qd)
	  to (12,   11,  9,    8,14,13,  2,  19,    1,3,18,4,17,5,16,6,    7,
	      15) ;
	}

part 54ls672 : default dil20 {
	newattr "$comment" = "4 Bit Univ. Shift Register/Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/s",rck,/sclr,s0,s1,sck,casc,srser,a,qa,b,qb,c,qc,d,slser,
	     qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/s",rck,/sclr,s0,s1,sck,casc,srser,a,qa,b,qb,c,qc,d,slser,
	      qd)
	  to (12,   11,  9,    8,14,13,  2,  19,    1,3,18,4,17,5,16,6,    7,
	      15) ;
	}

part 54ls673 : default dil24,dil24b {
	newattr "$comment" = "16 Bit SISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/strclr,mode,"r/w",/cs,clk,ser,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,
	     y10,y11,y12,y13,y14,y15) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/strclr,mode,"r/w",/cs,clk,ser,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,
	      y10,y11,y12,y13,y14,y15)
	  to (      4,   5,    3,  1,  2,  6, 7, 8, 9,10,11,13,14,15,16,17,
	       18, 19, 20, 21, 22, 23) ;
	}

part 54ls674 : default dil24,dil24b {
	newattr "$comment" = "16 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (mode,"r/w",/cs,clk,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,
	     p13,p14,p15,ser) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (mode,"r/w",/cs,clk,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,
	      p13,p14,p15,ser)
	  to (   5,    3,  1,  2, 7, 8, 9,10,11,13,14,15,16,17, 18, 19, 20,
	       21, 22, 23,  6) ;
	}

part 54ls681 : default dil20 {
	newattr "$comment" = "4 Bit Parallel Binary Accumulator" ;
	newattr "$ttlout" = "TP" ;
	pin (as0,as1,as2,m,cn,rs0,rs1,rs2,clk,/p,/g,"cn+4","ri/lo","li/ro",
	     io0,io1,io2,io3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (as0,as1,as2, m,cn,rs0,rs1,rs2,clk,/p,/g,"cn+4","ri/lo","li/ro",
	      io0,io1,io2,io3)
	  to ( 18, 17, 16,15, 6,  4,  3,  2,  1, 9, 7,     8,     19,      5,
	       14, 13, 12, 11) ;
	}

part 54ls682 : default dil20 {
	newattr "$comment" = "8 Bit Magnitude Comparator, 20k PullUp" ;
	newattr "$ttlout" = "TP" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q")
	  to ( 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19,     1) ;
	}

part 54ls683 : default dil20 {
	newattr "$comment" = "8 Bit Magnitude Comparator, 20k PullUp" ;
	newattr "$ttlout" = "OC" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q")
	  to ( 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19,     1) ;
	}

part 54ls684 : default dil20 {
	newattr "$comment" = "8 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "TS" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q")
	  to ( 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19,     1) ;
	}

part 54ls685 : default dil20 {
	newattr "$comment" = "8 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "OC" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q")
	  to ( 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19,     1) ;
	}

part 54ls686 : default dil24,dil24b {
	newattr "$comment" = "8 Bit Magnitude Comparator, Out Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (/g1,/g2,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q",
	     "/p>q") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g1,/g2,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q",
	      "/p>q")
	  to (  2, 23, 3, 5, 8,10,13,15,17,20, 4, 6, 9,11,14,16,18,21,    22,
	           1) ;
	}

part 54ls687 : default dil24,dil24b {
	newattr "$comment" = "8 Bit Magnitude Comparator, Out Enable" ;
	newattr "$ttlout" = "OC" ;
	pin (/g1,/g2,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q",
	     "/p>q") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g1,/g2,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q",
	      "/p>q")
	  to (  2, 23, 3, 5, 8,10,13,15,17,20, 4, 6, 9,11,14,16,18,21,    22,
	           1) ;
	}

part 54ls688 : default dil20 {
	newattr "$comment" = "8 Bit Identity Comparator, Output Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 54ls689 : default dil20 {
	newattr "$comment" = "8 Bit Identity Comparator, Output Enable" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),(11,12),(13,14),(15,16),(17,
	      18),19) ] ) ;
	}

part 54ls690 : default dil20 {
	newattr "$comment" = "Decade Counter Direct Clr, LS160A+Latch" ;
	pin (/g,"r/c",/rclr,rck,/cclr,/load,ent,enp,cck,/rco,a,qa,b,qb,c,
	     qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/c",/rclr,rck,/cclr,/load,ent,enp,cck,/rco,a,qa,b,qb,c,
	      qc,d,qd)
	  to (12,   11,    8,  9,    1,   13, 14,  7,  2,  19,3,18,4,17,5,
	      16,6,15) ;
	}

part 54ls691 : default dil20 {
	newattr "$comment" = "Binary Counter Direct Clr, LS161A+Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/c",/rclr,rck,/cclr,/load,ent,enp,cck,/rco,a,qa,b,qb,c,
	     qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/c",/rclr,rck,/cclr,/load,ent,enp,cck,/rco,a,qa,b,qb,c,
	      qc,d,qd)
	  to (12,   11,    8,  9,    1,   13, 14,  7,  2,  19,3,18,4,17,5,
	      16,6,15) ;
	}

part 54ls692 : default dil20 {
	newattr "$comment" = "Decade Counter Sync. Clear, LS162A+Latch" ;
	pin (/g,"r/c",/rclr,rck,/cclr,/load,ent,enp,cck,/rco,a,qa,b,qb,c,
	     qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/c",/rclr,rck,/cclr,/load,ent,enp,cck,/rco,a,qa,b,qb,c,
	      qc,d,qd)
	  to (12,   11,    8,  9,    1,   13, 14,  7,  2,  19,3,18,4,17,5,
	      16,6,15) ;
	}

part 54ls693 : default dil20 {
	newattr "$comment" = "Binary Counter Sync. Clear, LS163A+Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/c",/rclr,rck,/cclr,/load,ent,enp,cck,/rco,a,qa,b,qb,c,
	     qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/c",/rclr,rck,/cclr,/load,ent,enp,cck,/rco,a,qa,b,qb,c,
	      qc,d,qd)
	  to (12,   11,    8,  9,    1,   13, 14,  7,  2,  19,3,18,4,17,5,
	      16,6,15) ;
	}

part 54ls696 : default dil20 {
	newattr "$comment" = "Decade Up/Down Counter, Direct Clr Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/c",rck,/cclr,/load,"u/d",/ent,/enp,cck,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/c",rck,/cclr,/load,"u/d",/ent,/enp,cck,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (12,   11,  9,    8,   13,    1,  14,   7,  2,  19,3,18,4,17,
	      5,16,6,15) ;
	}

part 54ls697 : default dil20 {
	newattr "$comment" = "Binary Up/Down Counter, Direct Clr Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/c",rck,/cclr,/load,"u/d",/ent,/enp,cck,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/c",rck,/cclr,/load,"u/d",/ent,/enp,cck,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (12,   11,  9,    8,   13,    1,  14,   7,  2,  19,3,18,4,17,
	      5,16,6,15) ;
	}

part 54ls698 : default dil20 {
	newattr "$comment" = "Decade Up/Down Counter, Sync. Clr Latch" ;
	pin (/g,"r/c",rck,/cclr,/load,"u/d",/ent,/enp,cck,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/c",rck,/cclr,/load,"u/d",/ent,/enp,cck,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (12,   11,  9,    8,   13,    1,  14,   7,  2,  19,3,18,4,17,
	      5,16,6,15) ;
	}

part 54ls699 : default dil20 {
	newattr "$comment" = "Binary Up/Down Counter, Sync. Clr Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/c",rck,/cclr,/load,"u/d",/ent,/enp,cck,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/c",rck,/cclr,/load,"u/d",/ent,/enp,cck,/rco,a,qa,b,qb,
	      c,qc,d,qd)
	  to (12,   11,  9,    8,   13,    1,  14,   7,  2,  19,3,18,4,17,
	      5,16,6,15) ;
	}

part 54ls795 : default dil20 {
	newattr "$comment" = "Octal Buffer DM81LS95 Texas 74LS465" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2, 3, 4, 5, 6, 7, 8, 9,12,11,14,13,16,15,18,17) ;
	swap ( [  1,19,
	       ( 2, 3),
	       ( 4, 5),
	       ( 6, 7),
	       ( 8, 9),
	       (12,11),
	       (14,13),
	       (16,15),
	       (18,17) ] ) ;
	}

part 54ls796 : default dil20 {
	newattr "$comment" = "Octal Buffer DM81LS96 Texas 74LS466" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2, 3, 4, 5, 6, 7, 8, 9,12,11,14,13,16,15,18,17) ;
	swap ( [  1,19,
	       ( 2, 3),
	       ( 4, 5),
	       ( 6, 7),
	       ( 8, 9),
	       (12,11),
	       (14,13),
	       (16,15),
	       (18,17) ] ) ;
	}

part 54ls797 : default dil20 {
	newattr "$comment" = "Octal Buffer DM81LS97 Texas 74LS467" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2, 3, 4, 5, 6, 7, 8, 9)
	  or (19,12,11,14,13,16,15,18,17) ;
	swap ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), ( 8, 9) ],
	       [ 19, (12,11), (14,13), (16,15), (18,17) ] ) ;
	}

part 54ls798 : default dil20 {
	newattr "$comment" = "Octal Buffer DM81LS98 Texas 74LS468" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2, 3, 4, 5, 6, 7, 8, 9)
	  or (19,12,11,14,13,16,15,18,17) ;
	swap ( [  1, ( 2, 3), ( 4, 5), ( 6, 7), ( 8, 9) ],
	       [ 19, (12,11), (14,13), (16,15), (18,17) ] ) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.