loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d54h.def                                  */
/* SCM Library   : d54h.ddb                                  */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - Bipolar TTL High Speed / Series 54H                     */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 54  = Military (-55..125 Degree Celcius)  */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 54h00 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 54h01 : default dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 54h04 : default dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54h05 : default dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 54h10 : default dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 54h11 : default dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 54h15 : default dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 54h20 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54h21 : default dil14 {
	newattr "$comment" = "Dual 4 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54h22 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54h30 : default dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 54h40 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 54h50 : mainpart dil14 {
	newattr "$comment" = "Dual 2 Wide 2 Input AND-OR-Invert" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,x,/x,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b,c, d, x,/x,y)
	  to (1,13,9,10,11,12,8) ;
	swap ( [  (( 1,13)), (( 9,10)),11,12, 8 ] ) ;
	}

part 54h50x : subpart 54h50 {
	pin (a,b,c,d,y) ;
	xlat (a,b,c,d,y)
	  to (2,3,4,5,6) ;
	swap ( [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 54h51 : default dil14 {
	newattr "$comment" = "Dual 2 Wide 2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b,c, d,y)
	  to (1,13,9,10,8)
	  or (2, 3,4, 5,6) ;
	swap ( [  (( 1,13)), (( 9,10)), 8 ],
	       [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 54h53 : default dil14 {
	newattr "$comment" = "4 Wide 2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,x,/x,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b,c,d,e,f,g, h, x,/x,y)
	  to (1,13,2,3,4,5,9,10,11,12,8) ;
	swap internal ( (( 1,13)), (( 2, 3)), (( 4, 5)), (( 9,10)) ) ;
	}

part 54h54 : default dil14 {
	newattr "$comment" = "4 Wide 2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b,c,d,e,f,g, h,y)
	  to (1,13,2,3,4,5,9,10,8) ;
	swap internal ( (( 1,13)), (( 2, 3)), (( 4, 5)), (( 9,10)) ) ;
	}

part 54h60 : default dil14 {
	newattr "$comment" = "Dual 4 Input Expander" ;
	pin (a,b,c,d,x,/x) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c, d, x,/x)
	  to (1,2,3,13,11,12)
	  or (4,5,6, 8,10, 9) ;
	swap ( (( 1, 2, 3,13),11,12), (( 4, 5, 6, 8),10, 9) ) ;
	}

part 54h72 : default dil14 {
	newattr "$comment" = "J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j1,j2,j3,clk,k1,k2,k3,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,j1,j2,j3,clk,k1,k2,k3,/clr,q,/q)
	  to (  13, 3, 4, 5, 12, 9,10,11,   2,8, 6) ;
	}

part 54h73 : default dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (j,clk,k,/clr,q,/q) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat ( j,clk, k,/clr, q,/q)
	  to (14,  1, 3,   2,12,13)
	  or ( 7,  5,10,   6, 9, 8) ;
	swap ( (14, 1, 3, 2,12,13), ( 7, 5,10, 6, 9, 8) ) ;
	}

part 54h74 : default dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 54h76 : default dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (j,k,clk,/pre,/clr,q,/q) ;
	net "vss" : (13) ;
	net "vcc" : (5) ;
	xlat (j, k,clk,/pre,/clr, q,/q)
	  to (4,16,  1,   2,   3,15,14)
	  or (9,12,  6,   7,   8,11,10) ;
	swap ( ( 4,16, 1, 2, 3,15,14), ( 9,12, 6, 7, 8,11,10) ) ;
	}

part 54h78 : default dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Common Clear/Clock" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/clr,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat (clk,/clr,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (  1,   5,    2, 3,14,13, 12,    6,10, 7, 8,  9) ;
	swap internal ( ( 2, 3,14,13,12), ( 6,10, 7, 8, 9) ) ;
	}

part 54h160 : default dil16 {
	newattr "$comment" = "BCD Decade Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 54h259 : default dil16 {
	newattr "$comment" = "8 Bit Addressable Set-Reset Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,/g,d,/clr,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (s0,s1,s2,/g, d,/clr,q0,q1,q2,q3,q4,q5,q6,q7)
	  to ( 1, 2, 3,14,13,  15, 4, 5, 6, 7, 9,10,11,12) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.