loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d54bct.def                                */
/* SCM Library   : d54bct.ddb                                */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - BiCMOS (Bipolar CMOS) Bus Functions / Series 54BCT      */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 54  = Military (-55..125 Degree Celcius)  */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +5V DC                              */
/*___________________________________________________________*/


part 54bct125 : default dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 54bct126 : default dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 54bct240 : default dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54bct241 : default dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54bct244 : default dil20 {
	newattr "$comment" = "Octal Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54bct245 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54bct373 : default dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 54bct374 : default dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 54bct533 : default dil20 {
	newattr "$comment" = "Octal D-Type Latch inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1,11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 54bct534 : default dil20 {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to (  1, 11, 3,  2, 4,  5, 7,  6, 8,  9,13, 12,14, 15,17, 16,18,
	       19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 54bct540 : default dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 54bct541 : default dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,a1,y1,a2,y2,a3,y3,a4,y4,a5,y5,a6,y6,a7,y7,a8,y8)
	  to (  1, 19, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap internal ( (( 1,19)) ) ;
	swap internal ( ( 2,18),
	                ( 3,17),
	                ( 4,16),
	                ( 5,15),
	                ( 6,14),
	                ( 7,13),
	                ( 8,12),
	                ( 9,11) ) ;
	}

part 54bct543 : default dil24,dil24b {
	newattr "$comment" = "Octal Register Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	     b4,a5,b5,a6,b6,a7,b7) ;
	net "vss" : (18) ;
	net "vcc" : (6) ;
	xlat (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	      b4,a5,b5,a6,b6,a7,b7)
	  to (  17,   16,   21,  19,   20,   15,22,14,23,13,24,12, 1,11, 2,
	      10, 3, 9, 4, 8, 5, 7) ;
	}

part 54bct544 : default dil24,dil24b {
	newattr "$comment" = "Octal Register Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	     b4,a5,b5,a6,b6,a7,b7) ;
	net "vss" : (18) ;
	net "vcc" : (6) ;
	xlat (/eab,/leab,/oeab,/eba,/leba,/oeba,a0,b0,a1,b1,a2,b2,a3,b3,a4,
	      b4,a5,b5,a6,b6,a7,b7)
	  to (  17,   16,   21,  19,   20,   15,22,14,23,13,24,12, 1,11, 2,
	      10, 3, 9, 4, 8, 5, 7) ;
	}

part 54bct620 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54bct623 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54bct640 : default dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 54bct646 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54bct652 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 54bct757 : default dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54bct760 : default dil20 {
	newattr "$comment" = "Octal Bus Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54bct2240 : default dil20 {
	newattr "$comment" = "MOS Memory Driver type 240" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54bct2241 : default dil20 {
	newattr "$comment" = "MOS Memory Driver type 241" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 54bct2242 : default dil14 {
	newattr "$comment" = "MOS Memory Driver type 242" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 54bct2244 : default dil20 {
	newattr "$comment" = "MOS Memory Driver type 244" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.