loglib

/*___________________________________________________________*/
/*                                                           */
/* LOG Library   : d54ac11.def                               */
/* SCM Library   : d54ac11.ddb                               */
/*                                                           */
/* Author        : M. Baumeister, Bartels System             */
/* Last Revision : 1997/04/21                                */
/*                                                           */
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding          */
/*___________________________________________________________*/
/*                                                           */
/* This library provides definitions of                      */
/*                                                           */
/* - Advanced CMOS / EPIC center supply Series 54AC11        */
/*                                                           */
/* digital integrated circuits logic family.                 */
/*                                                           */
/* NOTES:                                                    */
/* Temperature   : 54  = Military (-55..125 Degree Celcius)  */
/* Power Supply  : vss = Digital Ground                      */
/*               : vcc = +2V to +6V DC                       */
/*___________________________________________________________*/


part 54ac11000 : default dil16 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	pin (a,b,y) ;
	net "vss" : (4,5) ;
	net "vcc" : (12,13) ;
	xlat ( a, b,y)
	  to ( 1,16,2)
	  or (15,14,3)
	  or (11,10,6)
	  or ( 9, 8,7) ;
	swap ( (( 1,16), 2),
	       ((15,14), 3),
	       ((11,10), 6),
	       (( 9, 8), 7) ) ;
	}

part 54ac11002 : default dil16 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	pin (a,b,y) ;
	net "vss" : (4,5) ;
	net "vcc" : (12,13) ;
	xlat ( a, b,y)
	  to ( 1,16,2)
	  or (15,14,3)
	  or (11,10,6)
	  or ( 9, 8,7) ;
	swap ( (( 1,16), 2),
	       ((15,14), 3),
	       ((11,10), 6),
	       (( 9, 8), 7) ) ;
	}

part 54ac11004 : default dil20 {
	newattr "$comment" = "Hex Inverter" ;
	pin (a,y) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat ( a, y)
	  to (20, 1)
	  or (19, 2)
	  or (18, 3)
	  or (13, 8)
	  or (12, 9)
	  or (11,10) ;
	swap ( (20, 1), (19, 2), (18, 3), (13, 8), (12, 9), (11,10) ) ;
	}

part 54ac11008 : default dil16 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	pin (a,b,y) ;
	net "vss" : (4,5) ;
	net "vcc" : (12,13) ;
	xlat ( a, b,y)
	  to ( 1,16,2)
	  or (15,14,3)
	  or (11,10,6)
	  or ( 9, 8,7) ;
	swap ( (( 1,16), 2),
	       ((15,14), 3),
	       ((11,10), 6),
	       (( 9, 8), 7) ) ;
	}

part 54ac11010 : default dil16 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	pin (a,b,c,y) ;
	net "vss" : (4,5) ;
	net "vcc" : (12,13) ;
	xlat ( a, b, c,y)
	  to ( 1,16,15,2)
	  or (14,11,10,3)
	  or ( 9, 8, 7,6) ;
	swap ( (( 1,16,15), 2), ((14,11,10), 3), (( 9, 8, 7), 6) ) ;
	}

part 54ac11011 : default dil16 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	pin (a,b,c,y) ;
	net "vss" : (4,5) ;
	net "vcc" : (12,13) ;
	xlat ( a, b, c,y)
	  to ( 1,16,15,2)
	  or (14,11,10,3)
	  or ( 9, 8, 7,6) ;
	swap ( (( 1,16,15), 2), ((14,11,10), 3), (( 9, 8, 7), 6) ) ;
	}

part 54ac11013 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Schmitt Trigger" ;
	pin (a,b,c,d,y) ;
	net "vss" : (4) ;
	net "vcc" : (11) ;
	xlat ( a,b, c, d,y)
	  to ( 2,1,13,12,3)
	  or (10,9, 7, 6,5) ;
	swap ( (( 2, 1,13,12), 3), ((10, 9, 7, 6), 5) ) ;
	}

part 54ac11014 : default dil20 {
	newattr "$comment" = "Hex Schmitt Trigger" ;
	pin (a,y) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat ( a, y)
	  to (20, 1)
	  or (19, 2)
	  or (18, 3)
	  or (13, 8)
	  or (12, 9)
	  or (11,10) ;
	swap ( (20, 1), (19, 2), (18, 3), (13, 8), (12, 9), (11,10) ) ;
	}

part 54ac11020 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	pin (a,b,c,d,y) ;
	net "vss" : (4) ;
	net "vcc" : (11) ;
	xlat ( a,b, c, d,y)
	  to ( 2,1,13,12,3)
	  or (10,9, 7, 6,5) ;
	swap ( (( 2, 1,13,12), 3), ((10, 9, 7, 6), 5) ) ;
	}

part 54ac11021 : default dil14 {
	newattr "$comment" = "Dual 4 Input AND Gate" ;
	pin (a,b,c,d,y) ;
	net "vss" : (4) ;
	net "vcc" : (11) ;
	xlat ( a,b, c, d,y)
	  to ( 2,1,13,12,3)
	  or (10,9, 7, 6,5) ;
	swap ( (( 2, 1,13,12), 3), ((10, 9, 7, 6), 5) ) ;
	}

part 54ac11027 : default dil16 {
	newattr "$comment" = "Triple 2 Input NOR Gate" ;
	pin (a,b,c,y) ;
	net "vss" : (4,5) ;
	net "vcc" : (12,13) ;
	xlat ( a, b, c,y)
	  to ( 1,16,15,2)
	  or (14,11,10,3)
	  or ( 9, 8, 7,6) ;
	swap ( (( 1,16,15), 2), ((14,11,10), 3), (( 9, 8, 7), 6) ) ;
	}

part 54ac11030 : default dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (4) ;
	net "vcc" : (11) ;
	xlat (a,b,c, d, e, f,g,h,y)
	  to (3,2,1,14,13,12,9,8,5) ;
	swap ( (( 3, 2, 1,14,13,12, 9, 8), 5) ) ;
	}

part 54ac11032 : default dil16 {
	newattr "$comment" = "Quad 2 Input OR Gate" ;
	pin (a,b,y) ;
	net "vss" : (4,5) ;
	net "vcc" : (12,13) ;
	xlat ( a, b,y)
	  to ( 1,16,2)
	  or (15,14,3)
	  or (11,10,6)
	  or ( 9, 8,7) ;
	swap ( (( 1,16), 2),
	       ((15,14), 3),
	       ((11,10), 6),
	       (( 9, 8), 7) ) ;
	}

part 54ac11034 : default dil20 {
	newattr "$comment" = "Hex Buffer" ;
	pin (a,y) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat ( a, y)
	  to (20, 1)
	  or (19, 2)
	  or (18, 3)
	  or (13, 8)
	  or (12, 9)
	  or (11,10) ;
	swap ( (20, 1), (19, 2), (18, 3), (13, 8), (12, 9), (11,10) ) ;
	}

part 54ac11074 : default dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (4) ;
	net "vcc" : (11) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   1, 14,13,  12,2, 3)
	  or (   7,  8, 9,  10,6, 5) ;
	swap ( ( 1,14,13,12, 2, 3), ( 7, 8, 9,10, 6, 5) ) ;
	}

part 54ac11109 : default dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	pin (/pre,j,clk,/k,/clr,q,/q) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (/pre, j,clk,/k,/clr,q,/q)
	  to (   1,14, 16,15,  13,2, 3)
	  or (   7,10,  8, 9,  11,6, 5) ;
	swap ( ( 1,14,16,15,13, 2, 3), ( 7,10, 8, 9,11, 6, 5) ) ;
	}

part 54ac11112 : default dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   1,16, 14,15,  13,2, 3)
	  or (   7, 8, 10, 9,  11,6, 5) ;
	swap ( ( 1,16,14,15,13, 2, 3), ( 7, 8,10, 9,11, 6, 5) ) ;
	}

part 54ac11132 : default dil16 {
	newattr "$comment" = "Quad 2 Input Schmitt Trigger" ;
	pin (a,b,y) ;
	net "vss" : (4,5) ;
	net "vcc" : (12,13) ;
	xlat ( a, b,y)
	  to ( 1,16,2)
	  or (15,14,3)
	  or (11,10,6)
	  or ( 9, 8,7) ;
	swap ( (( 1,16), 2),
	       ((15,14), 3),
	       ((11,10), 6),
	       (( 9, 8), 7) ) ;
	}

part 54ac11138 : default dil16 {
	newattr "$comment" = "3 of 8 Decoder" ;
	pin (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat ( a, b, c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (15,14,13,11,  10,   9,16, 1, 2, 3, 5, 6, 7, 8) ;
	swap internal ( ((10, 9)) ) ;
	}

part 54ac11139 : default dil16 {
	newattr "$comment" = "Dual 2 of 4 Decoder" ;
	pin (a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat ( a, b,/g,y0,y1,y2,y3)
	  to (15,14,13,16, 1, 2, 3)
	  or (10, 9,11, 5, 6, 7, 8) ;
	swap ( (15,14,13,16, 1, 2, 3), (10, 9,11, 5, 6, 7, 8) ) ;
	}

part 54ac11151 : default dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 2,6,7,8, 1,16,15,14,13,11,10, 9,3,5) ;
	}

part 54ac11153 : default dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (1,2,  6, 16, 15, 14, 13, 3,  7, 11, 10,  9,  8, 5) ;
	swap ( [  1, 2, ( 6,16,15,14,13, 3), ( 7,11,10, 9, 8, 5) ] ) ;
	}

part 54ac11157 : default dil20 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (10,  1,20,19, 2,18,17, 3,14,13, 8,12,11, 9) ;
	swap ( [ 10, 1,
	       (20,19, 2),
	       (18,17, 3),
	       (14,13, 8),
	       (12,11, 9) ] ) ;
	}

part 54ac11158 : default dil20 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (10,  1,20,19, 2,18,17, 3,14,13, 8,12,11, 9) ;
	swap ( [ 10, 1,
	       (20,19, 2),
	       (18,17, 3),
	       (14,13, 8),
	       (12,11, 9) ] ) ;
	}

part 54ac11160 : default dil20 {
	newattr "$comment" = "BCD Decade Counter, Direct Clear" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/clr,/load,ent,enp,clk,rco, a,qa, b,qb, c,qc, d,qd)
	  to (  20,   10, 11, 12, 19,  1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11161 : default dil20 {
	newattr "$comment" = "4 Bit Binary Counter, Direct Clear" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/clr,/load,ent,enp,clk,rco, a,qa, b,qb, c,qc, d,qd)
	  to (  20,   10, 11, 12, 19,  1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11162 : default dil20 {
	newattr "$comment" = "BCD Decade Counter, Sync. Clear" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/clr,/load,ent,enp,clk,rco, a,qa, b,qb, c,qc, d,qd)
	  to (  20,   10, 11, 12, 19,  1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11163 : default dil20 {
	newattr "$comment" = "4 Bit Binary Counter, Sync. Clear" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/clr,/load,ent,enp,clk,rco, a,qa, b,qb, c,qc, d,qd)
	  to (  20,   10, 11, 12, 19,  1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11168 : default dil20 {
	newattr "$comment" = "4 Bit Decade Up/Down Counter" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco, a,qa, b,qb, c,qc, d,qd)
	  to (   10,20,  11,  12, 19,   1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11169 : default dil20 {
	newattr "$comment" = "4 Bit Binary Up/Down Counter" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco, a,qa, b,qb, c,qc, d,qd)
	  to (   10,20,  11,  12, 19,   1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11174 : default dil20 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	pin (/clr,clk,d1,q1,d2,q2,d3,d4,q3,q4,d5,q5,d6,q6) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/clr,clk,d1,q1,d2,q2,d3,q3,d4,q4,d5,q5,d6,q6)
	  to (  20, 11,19, 1,18, 2,17, 3,14, 8,13, 9,12,10) ;
	swap ( [ 20,11,
	       (19, 1),
	       (18, 2),
	       (17, 3),
	       (14, 8),
	       (13, 9),
	       (12,10) ] ) ;
	}

part 54ac11175 : default dil20 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (  19, 12,18,20,  1,17, 2,  3,14, 8,  9,13,10, 11) ;
	swap ( [ 19,12,
	       (18,20, 1),
	       (17, 2, 3),
	       (14, 8, 9),
	       (13,10,11) ] ) ;
	}

part 54ac11181 : default dil28b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to (18,17,16,15,2, 1,12,13,    3,    14, 28, 24,  4, 27, 23,  5,
	       26, 20, 10, 25, 19, 11) ;
	}

part 54ac11190 : default dil20 {
	newattr "$comment" = "Synchronous Up/Down BCD Counter" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa, b,qb, c,qc, d,qd)
	  to (   12,20, 19,   11,    10,   1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11191 : default dil20 {
	newattr "$comment" = "Synchronous Up/Down Binary Counter" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa, b,qb, c,qc, d,qd)
	  to (   12,20, 19,   11,    10,   1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11192 : default dil20 {
	newattr "$comment" = "Sync. Up/Down Dual Clock BCD Counter" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa, b,qb, c,qc, d,qd)
	  to ( 12,19,  20,   11, 10,  1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11193 : default dil20 {
	newattr "$comment" = "Sync. Up/Down Dual Clock Binary Counter" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa, b,qb, c,qc, d,qd)
	  to ( 12,19,  20,   11, 10,  1,18, 2,17, 3,14, 8,13, 9) ;
	}

part 54ac11194 : default dil20 {
	newattr "$comment" = "4 Bit Universal Shift Register PIPO" ;
	pin (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/clr,s0,s1,clk,srser, a,qa, b,qb, c,qc, d,slser,qd)
	  to (  12,20,19, 11,    1,18, 2,17, 3,14, 8,13,   10, 9) ;
	}

part 54ac11238 : default dil16 {
	newattr "$comment" = "3 to 8 Bit Decoder/Demultiplexer" ;
	pin (a0,a1,a2,/e1,/e2,e3,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (a0,a1,a2,/e1,/e2,e3,q0,q1,q2,q3,q4,q5,q6,q7)
	  to (15,14,13, 10,  9,11,16, 1, 2, 3, 5, 6, 7, 8) ;
	swap internal ( ((10, 9)) ) ;
	}

part 54ac11239 : default dil16 {
	newattr "$comment" = "Dual 2 to 4 Bit Decoder/Demultiplexer" ;
	pin (a0,a1,/e,q0,q1,q2,q3) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (a0,a1,/e,q0,q1,q2,q3)
	  to (15,14,13,16, 1, 2, 3)
	  or (10, 9,11, 5, 6, 7, 8) ;
	swap ( (15,14,13,16, 1, 2, 3), (10, 9,11, 5, 6, 7, 8) ) ;
	}

part 54ac11240 : default dil24,dil24b {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to (24,23, 1,22, 2,21, 3,20, 4)
	  or (13,17, 9,16,10,15,11,14,12) ;
	swap ( [ 24, (23, 1), (22, 2), (21, 3), (20, 4) ],
	       [ 13, (17, 9), (16,10), (15,11), (14,12) ] ) ;
	}

part 54ac11241 : default dil24,dil24b {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to ( 24, 23,  1, 22,  2, 21,  3, 20,  4) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (13, 17,  9, 16, 10, 15, 11, 14, 12) ;
	swap internal ( [ 24, (23, 1), (22, 2), (21, 3), (20, 4) ] ) ;
	swap internal ( [ 13, (17, 9), (16,10), (15,11), (14,12) ] ) ;
	}

part 54ac11244 : default dil24,dil24b {
	newattr "$comment" = "Octal Driver noninverting" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to (24,23, 1,22, 2,21, 3,20, 4)
	  or (13,17, 9,16,10,15,11,14,12) ;
	swap ( [ 24, (23, 1), (22, 2), (21, 3), (20, 4) ],
	       [ 13, (17, 9), (16,10), (15,11), (14,12) ] ) ;
	}

part 54ac11245 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (13, 24, 1,23, 2,22, 3,21, 4,20, 9,17,10,16,11,15,12,14) ;
	swap ( [ 13,24,
	       ( 1,23),
	       ( 2,22),
	       ( 3,21),
	       ( 4,20),
	       ( 9,17),
	       (10,16),
	       (11,15),
	       (12,14) ] ) ;
	}

part 54ac11251 : default dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 2,6,7,8, 1,16,15,14,13,11,10, 9,3,5) ;
	}

part 54ac11253 : default dil16 {
	newattr "$comment" = "Dual 4 to 1 Multiplexer" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (1,2,  6, 16, 15, 14, 13, 3,  7, 11, 10,  9,  8, 5) ;
	swap ( [  1, 2, ( 6,16,15,14,13, 3), ( 7,11,10, 9, 8, 5) ] ) ;
	}

part 54ac11257 : default dil20 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (10, 1,20,19, 2,18,17, 3,14,13, 8,12,11, 9) ;
	swap ( [ 10, 1,
	       (20,19, 2),
	       (18,17, 3),
	       (14,13, 8),
	       (12,11, 9) ] ) ;
	}

part 54ac11258 : default dil20 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (10, 1,20,19, 2,18,17, 3,14,13, 8,12,11, 9) ;
	swap ( [ 10, 1,
	       (20,19, 2),
	       (18,17, 3),
	       (14,13, 8),
	       (12,11, 9) ] ) ;
	}

part 54ac11280 : default dil14 {
	newattr "$comment" = "9 Bit Odd/Even Parity Generator/Checker" ;
	pin (a,b,c,d,e,f,g,h,i,even,odd) ;
	net "vss" : (4) ;
	net "vcc" : (11) ;
	xlat (a,b, c, d, e, f,g,h,i,even,odd)
	  to (2,1,14,13,12,10,9,8,7,   5,  3) ;
	swap ( (( 2, 1,14,13,12,10, 9, 8, 7), 5, 3) ) ;
	}

part 54ac11286 : default dil14 {
	newattr "$comment" = "9 Bit Parity Generator/Checker" ;
	pin (a,b,c,d,e,f,g,h,i,/xmit,pario,parerr) ;
	net "vss" : (4) ;
	net "vcc" : (11) ;
	xlat (a,b, c, d, e, f,g,h,i,/xmit,pario,parerr)
	  to (2,1,14,13,12,10,9,8,7,    6,    3,     5) ;
	swap internal ( (( 2, 1,14,13,12,10, 9, 8, 7)) ) ;
	}

part 54ac11299 : default dil24,dil24b {
	newattr "$comment" = "8 Bit Universal PIPO Shift Register" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (  14, 21, 20,23,22, 15,16,     1,   24,     2,     3,     4,
	           9,    10,    11,    12,17,   13) ;
	swap internal ( ((21,20)) ) ;
	}

part 54ac11323 : default dil24,dil24b {
	newattr "$comment" = "8 Bit Shift/Storage Register" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (  14, 21, 20,23,22, 15,16,     1,   24,     2,     3,     4,
	           9,    10,    11,    12,17,   13) ;
	swap internal ( ((21,20)) ) ;
	}

part 54ac11352 : default dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (1,2,  6, 16, 15, 14, 13, 3,  7, 11, 10,  9,  8, 5) ;
	swap ( [  1, 2, ( 6,16,15,14,13, 3), ( 7,11,10, 9, 8, 5) ] ) ;
	}

part 54ac11353 : default dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (4) ;
	net "vcc" : (12) ;
	xlat (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (1,2,  6, 16, 15, 14, 13, 3,  7, 11, 10,  9,  8, 5) ;
	swap ( [  1, 2, ( 6,16,15,14,13, 3), ( 7,11,10, 9, 8, 5) ] ) ;
	}

part 54ac11373 : default dil24,dil24b {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to ( 24,13,23, 1,22, 2,21, 3,20, 4,17, 9,16,10,15,11,14,12) ;
	swap ( [ 24,13,
	       (23, 1),
	       (22, 2),
	       (21, 3),
	       (20, 4),
	       (17, 9),
	       (16,10),
	       (15,11),
	       (14,12) ] ) ;
	}

part 54ac11374 : default dil24,dil24b {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to ( 24, 13,23, 1,22, 2,21, 3,20, 4,17, 9,16,10,15,11,14,12) ;
	swap ( [ 24,13,
	       (23, 1),
	       (22, 2),
	       (21, 3),
	       (20, 4),
	       (17, 9),
	       (16,10),
	       (15,11),
	       (14,12) ] ) ;
	}

part 54ac11378 : default dil20 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q)
	  to ( 11,20,19, 1,18, 2,17, 3,14, 8,13, 9,12,10) ;
	swap ( [ 11,20,
	       (19, 1),
	       (18, 2),
	       (17, 3),
	       (14, 8),
	       (13, 9),
	       (12,10) ] ) ;
	}

part 54ac11379 : default dil20 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	pin (clk,/g,1d,1q,/1q,2d,2q,/2q,3d,3q,/3q,4d,4q,/4q) ;
	net "vss" : (4,5,6,7) ;
	net "vcc" : (15,16) ;
	xlat (clk,/g,1d,1q,/1q,2d,2q,/2q,3d,3q,/3q,4d,4q,/4q)
	  to ( 12,19,18,20,  1,17, 2,  3,14, 9,  8,13,11, 10) ;
	swap ( [ 12,19,
	       (18,20, 1),
	       (17, 2, 3),
	       (14, 9, 8),
	       (13,11,10) ] ) ;
	}

part 54ac11520 : default dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (5) ;
	net "vcc" : (15) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to (20, 4, 2,19,17,14,12,10, 8, 3, 1,18,16,13,11, 9, 7,     6) ;
	swap ( [ 20,
	       (( 4, 3),( 2, 1),(19,18),(17,16),(14,13),(12,11),(10, 9),( 8,
	       7), 6) ] ) ;
	}

part 54ac11521 : default dil20 {
	newattr "$comment" = "8 Bit Identity Comparator" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (5) ;
	net "vcc" : (15) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to (20, 4, 2,19,17,14,12,10, 8, 3, 1,18,16,13,11, 9, 7,     6) ;
	swap ( [ 20,
	       (( 4, 3),( 2, 1),(19,18),(17,16),(14,13),(12,11),(10, 9),( 8,
	       7), 6) ] ) ;
	}

part 54ac11533 : default dil24,dil24b {
	newattr "$comment" = "Octal D-Type Latch inverting" ;
	pin (/oc,c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,/8q) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/oc, c,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to ( 24,13,23,  1,22,  2,21,  3,20,  4,17,  9,16, 10,15, 11,14,
	       12) ;
	swap ( [ 24,13,
	       (23, 1),
	       (22, 2),
	       (21, 3),
	       (20, 4),
	       (17, 9),
	       (16,10),
	       (15,11),
	       (14,12) ] ) ;
	}

part 54ac11534 : default dil24,dil24b {
	newattr "$comment" = "Octal D-Type Flip-Flop inverting" ;
	pin (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	     /8q) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/oc,clk,1d,/1q,2d,/2q,3d,/3q,4d,/4q,5d,/5q,6d,/6q,7d,/7q,8d,
	      /8q)
	  to ( 24, 13,23,  1,22,  2,21,  3,20,  4,17,  9,16, 10,15, 11,14,
	       12) ;
	swap ( [ 24,13,
	       (23, 1),
	       (22, 2),
	       (21, 3),
	       (20, 4),
	       (17, 9),
	       (16,10),
	       (15,11),
	       (14,12) ] ) ;
	}

part 54ac11568 : default dil24,dil24b {
	newattr "$comment" = "4 Bit Decade Counter" ;
	pin (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco, a,qa, b,
	      qb, c,qc, d,qd)
	  to (11,   24, 23,  14,  15,   12,   13,   22,   2,   1,21, 3,20,
	       4,17, 9,16,10) ;
	}

part 54ac11569 : default dil24,dil24b {
	newattr "$comment" = "4 Bit Binary Counter" ;
	pin (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco,a,qa,b,qb,
	     c,qc,d,qd) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/g,"u/d",clk,/ent,/enp,/sclr,/load,/aclr,/cco,/rco, a,qa, b,
	      qb, c,qc, d,qd)
	  to (11,   24, 23,  14,  15,   12,   13,   22,   2,   1,21, 3,20,
	       4,17, 9,16,10) ;
	}

part 54ac11620 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  13, 24, 1,23, 2,22, 3,21, 4,20, 9,17,10,16,11,15,12,14) ;
	swap ( [ 13,24,
	       ( 1,23),
	       ( 2,22),
	       ( 3,21),
	       ( 4,20),
	       ( 9,17),
	       (10,16),
	       (11,15),
	       (12,14) ] ) ;
	}

part 54ac11623 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver" ;
	pin (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/gba,gab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (  13, 24, 1,23, 2,22, 3,21, 4,20, 9,17,10,16,11,15,12,14) ;
	swap ( [ 13,24,
	       ( 1,23),
	       ( 2,22),
	       ( 3,21),
	       ( 4,20),
	       ( 9,17),
	       (10,16),
	       (11,15),
	       (12,14) ] ) ;
	}

part 54ac11640 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (13, 24, 1,23, 2,22, 3,21, 4,20, 9,17,10,16,11,15,12,14) ;
	swap ( [ 13,24,
	       ( 1,23),
	       ( 2,22),
	       ( 3,21),
	       ( 4,20),
	       ( 9,17),
	       (10,16),
	       (11,15),
	       (12,14) ] ) ;
	}

part 54ac11643 : default dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver true inverting" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (5,6,7,8) ;
	net "vcc" : (18,19) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (13, 24, 1,23, 2,22, 3,21, 4,20, 9,17,10,16,11,15,12,14) ;
	swap ( [ 13,24,
	       ( 1,23),
	       ( 2,22),
	       ( 3,21),
	       ( 4,20),
	       ( 9,17),
	       (10,16),
	       (11,15),
	       (12,14) ] ) ;
	}

part 54ac11646 : default dil28b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to ( 1, 14, 16, 15, 28, 27, 2,26, 3,25, 4,24, 5,23,10,20,11,19,
	      12,18,13,17) ;
	swap ( [  1,14,16,15,28,27,
	       ( 2,26),
	       ( 3,25),
	       ( 4,24),
	       ( 5,23),
	       (10,20),
	       (11,19),
	       (12,18),
	       (13,17) ] ) ;
	}

part 54ac11648 : default dil28b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to ( 1, 14, 16, 15, 28, 27, 2,26, 3,25, 4,24, 5,23,10,20,11,19,
	      12,18,13,17) ;
	swap ( [  1,14,16,15,28,27,
	       ( 2,26),
	       ( 3,25),
	       ( 4,24),
	       ( 5,23),
	       (10,20),
	       (11,19),
	       (12,18),
	       (13,17) ] ) ;
	}

part 54ac11651 : default dil28b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  14,  1, 16, 15, 28, 27, 2,26, 3,25, 4,24, 5,23,10,20,11,19,
	      12,18,13,17) ;
	swap ( [ 14, 1,16,15,28,27,
	       ( 2,26),
	       ( 3,25),
	       ( 4,24),
	       ( 5,23),
	       (10,20),
	       (11,19),
	       (12,18),
	       (13,17) ] ) ;
	}

part 54ac11652 : default dil28b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  14,  1, 16, 15, 28, 27, 2,26, 3,25, 4,24, 5,23,10,20,11,19,
	      12,18,13,17) ;
	swap ( [ 14, 1,16,15,28,27,
	       ( 2,26),
	       ( 3,25),
	       ( 4,24),
	       ( 5,23),
	       (10,20),
	       (11,19),
	       (12,18),
	       (13,17) ] ) ;
	}

part 54ac11821 : default dil28b {
	newattr "$comment" = "10 Bit D-FF/Register" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	     10d,10q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,
	      9q,10d,10q)
	  to ( 28, 15,27, 1,26, 2,25, 3,24, 4,23, 5,20,10,19,11,18,12,17,
	      13, 16, 14) ;
	swap ( [ 28,15,
	       (27, 1),
	       (26, 2),
	       (25, 3),
	       (24, 4),
	       (23, 5),
	       (20,10),
	       (19,11),
	       (18,12),
	       (17,13),
	       (16,14) ] ) ;
	}

part 54ac11822 : default dil28b {
	newattr "$comment" = "10 Bit D-FF/Register inverting" ;
	pin (/oc,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	     8q,/9d,9q,/10d,10q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	      8q,/9d,9q,/10d,10q)
	  to ( 28, 15, 27, 1, 26, 2, 25, 3, 24, 4, 23, 5, 20,10, 19,11, 18,
	      12, 17,13,  16, 14) ;
	swap ( [ 28,15,
	       (27, 1),
	       (26, 2),
	       (25, 3),
	       (24, 4),
	       (23, 5),
	       (20,10),
	       (19,11),
	       (18,12),
	       (17,13),
	       (16,14) ] ) ;
	}

part 54ac11823 : default dil28b {
	newattr "$comment" = "9 Bit D-FF/Register" ;
	pin (/oc,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,
	     8d,8q,9d,9q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,
	      7q,8d,8q,9d,9q)
	  to ( 28,  14,    16, 15,27, 1,26, 2,25, 3,24, 4,23, 5,20,10,19,
	      11,18,12,17,13) ;
	swap ( [ 28,14,16,15,
	       (27, 1),
	       (26, 2),
	       (25, 3),
	       (24, 4),
	       (23, 5),
	       (20,10),
	       (19,11),
	       (18,12),
	       (17,13) ] ) ;
	}

part 54ac11824 : default dil28b {
	newattr "$comment" = "9 Bit D-FF/Register inverting" ;
	pin (/oc,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,
	     /7d,7q,/8d,8q,/9d,9q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,
	      6q,/7d,7q,/8d,8q,/9d,9q)
	  to ( 28,  14,    16, 15, 27, 1, 26, 2, 25, 3, 24, 4, 23, 5, 20,
	      10, 19,11, 18,12, 17,13) ;
	swap ( [ 28,14,16,15,
	       (27, 1),
	       (26, 2),
	       (25, 3),
	       (24, 4),
	       (23, 5),
	       (20,10),
	       (19,11),
	       (18,12),
	       (17,13) ] ) ;
	}

part 54ac11825 : default dil28b {
	newattr "$comment" = "Octal Register noninv" ;
	pin (/oc1,/oc2,/oc3,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,
	     6d,6q,7d,7q,8d,8q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc1,/oc2,/oc3,/clr,/clken,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,
	      6d,6q,7d,7q,8d,8q)
	  to (   1,  28,  27,  14,    16, 15,26, 2,25, 3,24, 4,23, 5,20,10,
	      19,11,18,12,17,13) ;
	swap internal ( (( 1,28,27)) ) ;
	swap internal ( (26, 2),
	                (25, 3),
	                (24, 4),
	                (23, 5),
	                (20,10),
	                (19,11),
	                (18,12),
	                (17,13) ) ;
	}

part 54ac11826 : default dil28b {
	newattr "$comment" = "Octal Register inverting" ;
	pin (/oc1,/oc2,/oc3,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,
	     5q,/6d,6q,/7d,7q,/8d,8q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc1,/oc2,/oc3,/clr,/clken,clk,/1d,1q,/2d,2q,/3d,3q,/4d,4q,
	      /5d,5q,/6d,6q,/7d,7q,/8d,8q)
	  to (   1,  28,  27,  14,    16, 15, 26, 2, 25, 3, 24, 4, 23, 5,
	       20,10, 19,11, 18,12, 17,13) ;
	swap internal ( (( 1,28,27)) ) ;
	swap internal ( (26, 2),
	                (25, 3),
	                (24, 4),
	                (23, 5),
	                (20,10),
	                (19,11),
	                (18,12),
	                (17,13) ) ;
	}

part 54ac11841 : default dil28b {
	newattr "$comment" = "10 Bit Transparent Latch" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	     10d,10q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q,9d,9q,
	      10d,10q)
	  to ( 28,15,27, 1,26, 2,25, 3,24, 4,23, 5,20,10,19,11,18,12,17,13,
	       16, 14) ;
	swap ( [ 28,15,
	       (27, 1),
	       (26, 2),
	       (25, 3),
	       (24, 4),
	       (23, 5),
	       (20,10),
	       (19,11),
	       (18,12),
	       (17,13),
	       (16,14) ] ) ;
	}

part 54ac11842 : default dil28b {
	newattr "$comment" = "10 Bit Transparent Latch inverting" ;
	pin (/oc,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,8q,
	     /9d,9q,/10d,10q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,7q,/8d,
	      8q,/9d,9q,/10d,10q)
	  to ( 28,15, 27, 1, 26, 2, 25, 3, 24, 4, 23, 5, 20,10, 19,11, 18,
	      12, 17,13,  16, 14) ;
	swap ( [ 28,15,
	       (27, 1),
	       (26, 2),
	       (25, 3),
	       (24, 4),
	       (23, 5),
	       (20,10),
	       (19,11),
	       (18,12),
	       (17,13),
	       (16,14) ] ) ;
	}

part 54ac11843 : default dil28b {
	newattr "$comment" = "9 Bit Transparent Latch" ;
	pin (/oc,/clr,/pre,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,
	     8q,9d,9q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc,/clr,/pre, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,
	      8d,8q,9d,9q)
	  to ( 28,  14,  16,15,27, 1,26, 2,25, 3,24, 4,23, 5,20,10,19,11,
	      18,12,17,13) ;
	swap ( [ 28,14,16,15,
	       (27, 1),
	       (26, 2),
	       (25, 3),
	       (24, 4),
	       (23, 5),
	       (20,10),
	       (19,11),
	       (18,12),
	       (17,13) ] ) ;
	}

part 54ac11844 : default dil28b {
	newattr "$comment" = "9 Bit Transparent Latch inverting" ;
	pin (/oc,/clr,/pre,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,/7d,
	     7q,/8d,8q,/9d,9q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc,/clr,/pre, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,/6d,6q,
	      /7d,7q,/8d,8q,/9d,9q)
	  to ( 28,  14,  16,15, 27, 1, 26, 2, 25, 3, 24, 4, 23, 5, 20,10,
	       19,11, 18,12, 17,13) ;
	swap ( [ 28,14,16,15,
	       (27, 1),
	       (26, 2),
	       (25, 3),
	       (24, 4),
	       (23, 5),
	       (20,10),
	       (19,11),
	       (18,12),
	       (17,13) ] ) ;
	}

part 54ac11845 : default dil28b {
	newattr "$comment" = "Octal Latch noninv" ;
	pin (/oc1,/oc2,/oc3,/pre,/clr,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,
	     6q,7d,7q,8d,8q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc1,/oc2,/oc3,/pre,/clr, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,
	      6q,7d,7q,8d,8q)
	  to (   1,  28,  27,  16,  14,15,26, 2,25, 3,24, 4,23, 5,20,10,19,
	      11,18,12,17,13) ;
	swap internal ( (( 1,28,27)) ) ;
	swap internal ( (26, 2),
	                (25, 3),
	                (24, 4),
	                (23, 5),
	                (20,10),
	                (19,11),
	                (18,12),
	                (17,13) ) ;
	}

part 54ac11846 : default dil28b {
	newattr "$comment" = "Octal Latch inverting" ;
	pin (/oc1,/oc2,/oc3,/pre,/clr,c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,5q,
	     /6d,6q,/7d,7q,/8d,8q) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc1,/oc2,/oc3,/pre,/clr, c,/1d,1q,/2d,2q,/3d,3q,/4d,4q,/5d,
	      5q,/6d,6q,/7d,7q,/8d,8q)
	  to (   1,  28,  27,  16,  14,15, 26, 2, 25, 3, 24, 4, 23, 5, 20,
	      10, 19,11, 18,12, 17,13) ;
	swap internal ( (( 1,28,27)) ) ;
	swap internal ( (26, 2),
	                (25, 3),
	                (24, 4),
	                (23, 5),
	                (20,10),
	                (19,11),
	                (18,12),
	                (17,13) ) ;
	}

part 54ac11873 : default dil28b {
	newattr "$comment" = "Octal Transparent Latch" ;
	pin (/oc,c,/clr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc, c,/clr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to ( 28, 1,  27,26, 2,25, 3,24, 4,23, 5)
	  or ( 15,14,  16,20,10,19,11,18,12,17,13) ;
	swap ( [ 28, 1,27, (26, 2), (25, 3), (24, 4), (23, 5) ],
	       [ 15,14,16, (20,10), (19,11), (18,12), (17,13) ] ) ;
	}

part 54ac11874 : default dil28b {
	newattr "$comment" = "Flip-Flop Octal D-Type" ;
	pin (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (/oc,clk,/clr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to ( 28,  1,  27,26, 2,25, 3,24, 4,23, 5)
	  or ( 15, 14,  16,20,10,19,11,18,12,17,13) ;
	swap ( [ 28, 1,27, (26, 2), (25, 3), (24, 4), (23, 5) ],
	       [ 15,14,16, (20,10), (19,11), (18,12), (17,13) ] ) ;
	}

part 54ac11881 : default dil28b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to (18,17,16,15,2, 1,12,13,    3,    14, 28, 24,  4, 27, 23,  5,
	       26, 20, 10, 25, 19, 11) ;
	}

part 54ac11882 : default dil28b {
	newattr "$comment" = "32 Bit Look-Ahead Carry Generator" ;
	pin (cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,/p4,/g4,/p5,/g5,/p6,/g6,/p7,
	     /g7,"cn+8","cn+16","cn+24","cn+32") ;
	net "vss" : (6,7,8,9) ;
	net "vcc" : (21,22) ;
	xlat (cn,/p0,/g0,/p1,/g1,/p2,/g2,/p3,/g3,/p4,/g4,/p5,/g5,/p6,/g6,
	      /p7,/g7,"cn+8","cn+16","cn+24","cn+32")
	  to ( 3,  2,  1, 28, 27, 26, 25, 24, 23, 20, 19, 18, 17, 16, 15,
	       14, 13,     4,      5,     10,     11) ;
	}

/*___________________________________________________________*/
/* Logical Library definition file end */

end.