loglib

/*______________________________________________________________*/
/*								*/
/* LOG Library	: cypress.def					*/
/* SCM Library	: cypress.ddb					*/
/*								*/
/* Author	: Bartels System				*/
/* Last Revision: 2005/02/15					*/
/*______________________________________________________________*/
/*								*/
/* This library includes circuit families manufactured by	*/
/* Cypress Semiconductor such as				*/
/*								*/
/*	- Memory Devices					*/
/*	- PLL Circuits						*/
/*								*/
/* NOTE:							*/
/*								*/
/* The part names used in this library DO NOT include  suffixes	*/
/* referring to temperature range, timing constraints, plastic	*/
/* or ceramic DIL packages (as long as pin compatibility is	*/
/* maintained).							*/
/*______________________________________________________________*/

/*______________________________________________________________*/
/* Memory Devices */

/* Programmable Read Only Memory (PROMs) */

part cy7c245 : dil24s {
	newattr "$comment" = "Reprogrammable Registered PROM 2048 x 8" ;
	newattr "$commentge" = "Register-PROM 2048 x 8 reprogrammierbar" ;
	newattr "$type" = "CY7C245" ;
	newattr "$manufacturer" = "Cypress Semiconductor" ;
	pin (o0,o1,o2,o3,o4,o5,o6,o7,"/e/es",/init,cp) ;
	bus (abus) ;
	net "vcc" : (24) ;
	net "vss" : (12) ;
	xlat (o0,o1,o2,o3,o4,o5,o6,o7,"/e/es",/init,cp)
	  to ( 9,10,11,13,14,15,16,17,     19,   20,18) ;
	xlat (abus.a0,abus.a1,abus.a2,abus.a3, abus.a4,abus.a5,
	      abus.a6,abus.a7,abus.a8,abus.a9,abus.a10)
	  to (      8,      7,      6,      5,       4,      3,
	            2,      1,     23,     22,      21) ;
	}

part cy7c291 : dil24b {
	newattr "$comment" = "Reprogrammable PROM 2048 x 8" ;
	newattr "$commentge" = "PROM 2048 x 8 reprogrammierbar" ;
	newattr "$type" = "CY7C291" ;
	newattr "$manufacturer" = "Cypress Semiconductor" ;
	pin (/cs1,cs2,cs3,
	     a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,
	     q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "gnd" : (12) ;
	net "vcc" : (24) ;
	xlat (/cs1,cs2,cs3,
	      a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,
	      q0,q1,q2,q3,q4,q5,q6,q7)
	   to ( 20, 19, 18,
	       8, 7, 6, 5, 4, 3, 2, 1,23,22, 21,
	       9,10,11,13,14,15,16,17) ;
	}

part cy7c292 : dil24b {
	newattr "$comment" = "Reprogrammable PROM 2048 x 8" ;
	newattr "$commentge" = "PROM 2048 x 8 reprogrammierbar" ;
	newattr "$type" = "CY7C292" ;
	newattr "$manufacturer" = "Cypress Semiconductor" ;
	pin (/cs1,cs2,cs3,
	     a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,
	     q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "gnd" : (12) ;
	net "vcc" : (24) ;
	xlat (/cs1,cs2,cs3,
	      a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,
	      q0,q1,q2,q3,q4,q5,q6,q7)
	  to (  20, 19, 18,
	       8, 7, 6, 5, 4, 3, 2, 1,23,22, 21,
	       9,10,11,13,14,15,16,17) ;
	}

/* FIFO Buffer Components */

part cy7c432 : dil28ft {
	newattr "$comment" = "4K x 9 FIFO" ;
	newattr "$type" = "CY7C432" ;
	newattr "$manufacturer" = "Cypress Semiconductor" ;
	pin (d0,d1,d2,d3,d4,d5,d6,d7,d8,
	     q0,q1,q2,q3,q4,q5,q6,q7,q8,
	     /w,/mr,/xi,"/fl/rt",/r,/ef,/ff,"/xo/hf") ;
	net "vcc" : (28) ;
	net "vss" : (14) ;
	xlat (d0,d1,d2,d3,d4,d5,d6,d7,d8,
	      q0,q1,q2,q3,q4,q5,q6,q7,q8,
	      /w,/mr,/xi,"/fl/rt",/r,/ef,/ff,"/xo/hf")
	  to ( 6, 5, 4, 3,27,26,25,24, 2,
	       9,10,11,12,16,17,18,19,13,
	       1, 22,  7,      23,15, 21,  8,      20) ;
	}

part cy7c4211 : plcc32 {
	newattr "$comment" = "FIFO 512 x 9 sync." ;
	newattr "$type" = "CY7C4211" ;
	pin (d0,d1,d2,d3,d4,d5,d6,d7,d8,
	 q0,q1,q2,q3,q4,q5,q6,q7,q8,
	 rclk,/ren1,/ren2,/oe,wclk,/wen1,wen2,/rs,
	 /ef,/pae,/paf,/ff) ;
	net "vcc" : (25) ;
	net "vss" : (9) ;
	xlat (d0,d1,d2,d3,d4,d5,d6,d7,d8,
	      q0,q1,q2,q3,q4,q5,q6,q7,q8,
	      rclk,/ren1,/ren2,/oe,wclk,/wen1,wen2,/rs,
	      /ef,/pae,/paf,/ff)
	  to ( 6, 5, 4, 3, 2, 1,32,31,30,
	      16,17,18,19,20,21,22,23,24,
	        11,   10,   12, 13,  27,   28,  26, 29,
	      14,   8,   7, 15) ;
	}

/* RAMs */

part cy62256 : so28 {
	newattr "$comment" = "SRAM 32K x 8" ;
	newattr "$commentge" = "SRAM 32K x 8" ;
	newattr "$type" = "CY62256" ;
	newattr "$manufacturer" = "Cypress" ;
	pin (a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,
	 d0,d1,d2,d3,d4,d5,d6,d7,/ce,/oe,/we,vcc,vss) ;
	xlat (a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,
	      d0,d1,d2,d3,d4,d5,d6,d7,/ce,/oe,/we,vcc,vss)
	  to ( 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 21, 23, 24, 25, 26,
	      11,12,13,15,16,17,18,19, 20, 22, 27, 28, 14);
	swap internal (((1)),((2)),((3)),((4)),((5)),((6)),((7)),
	 ((8)),((9)),((10)),((21)),((23)),((24)),((25)),((26)));
	swap internal (((11)),((12)),((13)),((15)),
	 ((16)),((17)),((18)),((19)));
	}

/*______________________________________________________________*/
/* Clock PLL circuits */

part cy2308 : so16 {
	newattr "$comment" = "3.3V Zero Delay Clock Buffer" ;
	newattr "$commentge" = "3,3V Zero Delay Takttreiber" ;
	newattr "$type" = "CY2308" ;
	newattr "$manufacturer" = "Cypress" ;
	pin (ref,fbk,s1,s2,
	     clka1,clka2,clka3,clka4,clkb1,clkb2,clkb3,clkb4);
	xlat (ref,fbk,s1,s2,
	      clka1,clka2,clka3,clka4,clkb1,clkb2,clkb3,clkb4)
	  to (  1, 16, 9, 8,
	          2,    3,   14,   15,    6,    7,   10,   11);
	net "vcc33" : (4,13);
	net "vss" : (5,12);
	}

part cy22393 : tssop16 {
	newattr "$comment" = "PLL Clock Generator" ;
	newattr "$commentge" = "PLL Taktgenerator" ;
	newattr "$type" = "CY22393" ;
	newattr "$manufacturer" = "Cypress" ;
	pin (xin,xout,/shut,/susp,sdat,sclk,
	     xbuf,clka,clkb,clkc,clkd,clke,avcc33,avss);
	xlat (xin,xout,/shut,/susp,sdat,sclk,
	      xbuf,clka,clkb,clkc,clkd,clke,avcc33,avss)
	  to (  4,   5,   16,   15,  12,  13,
	         6,  10,   9,   1,   7,   8,    14,   3);
	net "vcc33" : (2);
	net "vss" : (11);
	}

/*______________________________________________________________*/
/* Logical Library definition file end */

end.