loglib

/*______________________________________________________________*/
/*								*/
/* LOG Library	: cmos.def					*/
/* SCM Library	: cmos.ddb					*/
/*								*/
/* Author	: Bartels System				*/
/* Last Revision: 03/07/25					*/
/*______________________________________________________________*/
/*								*/
/* This library contains definitions of digital integrated	*/
/* circuits logic family					*/
/*								*/
/*	- Standard CMOS / Series 4000 B				*/
/*								*/
/* usually to be provided by manufacturers such as		*/
/*								*/
/*	- Harris Semiconductor/Intersil (cd*)			*/
/*	- Motorola (mc*)					*/
/*	- Philips (hef*)					*/
/*	- SGS Thomson (hcf*)					*/
/*	- et. al.						*/
/*								*/
/* NOTE:							*/
/*								*/
/* The part names used in this library NEITHER do include	*/
/* prefixes referring to the manufacturer NOR do they include	*/
/* suffixes referring to temperature range, timing constraints, */
/* package type such as plastic or ceramic DIL, or SO (as long	*/
/* as pin compatibility is maintained).				*/
/*								*/
/* CONVENTIONS:							*/
/*								*/
/* 1.	The library parts identified by the usual 4*** number	*/
/*	(without manufacturer prefix or package type suffix)	*/
/*	correspond to the entire CMOS package or one of several	*/
/*	independent IDENTICAL circuits.				*/
/*								*/
/* 2.	Mainpart/subpart definitions are provided for packages	*/
/*	containing two or more independent, but DIFFERENT	*/
/*	circuits. These library parts are either named 4***	*/
/*	(mainpart) and 4***s (subpart), or 4***a, 4***b, etc.	*/
/*	in the order of decreasing number of circuits per	*/
/*	package and decreasing complexity.			*/
/*								*/
/* 3.	Power pins are connected to nets "vss" and "vee".	*/
/*								*/
/* 4.	An effort has been made to make symbols for parts with	*/
/*	similar functions (e.g., gates, bus circuits) as	*/
/*	similar as possible. All pins are usually placed in a	*/
/*	2mm grid and the usual distance between adjacent pins	*/
/*	(of the symbol!) is 4mm.				*/
/*								*/
/* 5.	The design of part symbols complies with the following	*/
/*	rules wherever this is not unreasonable:		*/
/*	(a) inputs are on the left, outputs on the right,	*/
/*	(b) control lines are below data or address lines,	*/
/*	(c) data lines are below address lines,			*/
/*	(d) lines corresponding to more significant bits are	*/
/*	    below those corresponding to less significant,	*/
/*	(e) inverting inputs(outputs) are below non-inverting	*/
/*	    lines,						*/
/*	(f) clocks are below set/reset and enable lines.	*/
/*______________________________________________________________*/

/*______________________________________________________________*/
/* Gates NOR/ NAND */

part 4000 : mainpart default dil14,so14 {
	newattr "$comment" = "Dual 3-Input NOR Gate plus Inverter" ;
	pin (a,b,c,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, y)
	  to ( 3, 4, 5, 6)
	  or (11,12,13,10) ;
	swap (((3,4,5),6), ((11,12,13),10)) ;
	}
part 4000i : subpart 4000 {
	pin (a,y) ;
	xlat (a,y)
	  to (8,9) ;
	}

part 4001 : default dil14,so14 {
	newattr "$comment" = "Quad 2-Input NOR Gate" ;
	pin (a,b,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 6, 5, 4)
	  or ( 8, 9,10)
	  or (13,12,11) ;
	swap (((1,2),3), ((6,5),4), ((8,9),10), ((13,12),11)) ;
	}

part 4002 : default dil14,so14 {
	newattr "$comment" = "Dual 4-Input NOR-Gate" ;
	pin (a,b,c,d,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, d, y)
	  to ( 2, 3, 4, 5, 1)
	  or ( 9,10,11,12,13) ;
	swap (((2,3,4,5),1), ((9,10,11,12),13)) ;
	}

part 4006 : default dil14,so14 {
	newattr "$comment" = "18-Stage Static Shift Register" ;
	pin (1,2,3,4,5,6,8,9,10,11,12,13) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	}

part 4008 : default dil16 {
	newattr "$comment" = "4-Bit Full Adder with Parallel Carry" ;
	pin (b4,a4,b3,a3,b2,a2,b1,a1,ci,co,s4,s3,s2,s1) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (b4,a4,b3,a3,b2,a2,b1,a1,ci,co,s4,s3,s2,s1)
	  to (15, 1, 2, 3, 4, 5, 6, 7, 9,14,13,12,11,10) ;
	}

part 4009a : mainpart default dil16 {
	newattr "$comment" = "Hex Buffer/Converter (inverting)" ;
	pin (a,y,v) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (a,y,v) to (3,2,1) ;
	}
part 4009b : subpart 4009a {
	pin (a,y) ;
	xlat ( a, y)
	  to ( 5, 4)
	  or ( 7, 6)
	  or ( 9,10)
	  or (11,12)
	  or (14,15) ;
	swap ((5,4), (7,6), (9,10), (11,12), (14,15)) ;
	}

part 4010a : mainpart default dil16 {
	newattr "$comment" = "Hex Buffer/Converter (non-inverting)" ;
	pin (a,y,v) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (a,y,v) to (3,2,1) ;
	}
part 4010b : subpart 4010a {
	pin (a,y) ;
	xlat ( a, y)
	  to ( 5, 4)
	  or ( 7, 6)
	  or ( 9,10)
	  or (11,12)
	  or (14,15) ;
	swap ((5,4), (7,6), (9,10), (11,12), (14,15)) ;
	}

part 4011 : default dil14,so14 {
	newattr "$comment" = "Quad 2-Input NAND Gate" ;
	pin (a,b,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 6, 5, 4)
	  or ( 8, 9,10)
	  or (13,12,11) ;
	swap (((1,2),3), ((6,5),4), ((8,9),10), ((13,12),11)) ;
	}

part 4012 : default dil14,so14 {
	newattr "$comment" = "Dual 4-Input NAND Gate" ;
	pin (a,b,c,d,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, d, y)
	  to ( 2, 3, 4, 5, 1)
	  or ( 9,10,11,12,13) ;
	swap (((2,3,4,5),1), ((9,10,11,12),13)) ;
	}

part 4013 : default dil14,so14 {
	newattr "$comment" = "Dual D Flip-Flop with Set/Reset" ;
	pin (d,c,s,r,q,/q) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( d, c, s, r, q,/q)
	  to ( 5, 3, 6, 4, 1, 2)
	  or ( 9,11, 8,10,13,12) ;
	swap ((5,3,6,4,1,2), (9,11,8,10,13,12)) ;
	}

part 4014 : default dil16 {
	newattr "$comment" = "8-Stage Static Shift Register" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4015 : default dil16 {
	newattr "$comment" = "Dual 4-Stage Static Shift Register" ;
	pin (d,clk,rs,q1,q2,q3,q4) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( d,clk,rs,q1,q2,q3,q4)
	  to ( 7,  9, 6, 5, 4, 3,10)
	  or (15,  1,14,13,12,11, 2) ;
	swap ((7,9,6,5,4,3,10), (15,1,14,13,12,11,2)) ;
	}

part 4016 : default dil14,so14 {
	newattr "$comment" = "Quad Bilateral Switch" ;
	pin (a,b,s) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, s)
	  to ( 1, 2,13)
	  or ( 3, 4, 5)
	  or ( 8, 9, 6)
	  or (10,11,12) ;
	swap (((1,2),13), ((3,4),5), ((8,9),6), ((10,11),12)) ;
	}

part 4017 : default dil16 {
	newattr "$comment" = "Decade Counter/Divider" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4018 : default dil16 {
	newattr "$comment" = "Presettable Divide-by-N Counter" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4019 : mainpart default dil16 {
	newattr "$comment" = "Qud AND-OR Select Gate" ;
	pin (a,b,d) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( a, b, d)
	  to (15, 1,13)
	  or ( 2, 3,12)
	  or ( 4, 5,11)
	  or ( 6, 7,10) ;
	swap ((15,1,13), (2,3,12), (4,5,11), (6,7,10)) ;
	}
part 4019s : subpart 4019 {
	pin (9,14) ;
	}

part 4020 : default dil16 {
	newattr "$comment" = "14-Stage Binary Ripple Counter" ;
	pin (in,rs,q1,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (in,rs,q1,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14)
	  to (10,11, 9, 7, 5, 4, 6,13,12, 14, 15,  1,  2,  3) ;
	}

part 4021 : default dil16 {
	newattr "$comment" = "8-Stage Static Shift Register" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4022 : default dil16 {
	newattr "$comment" = "Divide-by-8 Counter/Divider" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4023 : default dil14,so14 {
	newattr "$comment" = "Triple 3-Input NAND Gate" ;
	pin (a,b,c,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, y)
	  to ( 3, 4, 5, 6)
	  or ( 1, 2, 8, 9)
	  or (11,12,13,10) ;
	swap (((3,4,5),6), ((1,2,8),9), ((11,12,13),10)) ;
	}

part 4024 : default dil14,so14 {
	newattr "$comment" = "7-Stage Binary Counter" ;
	pin (in,rs,q1,q2,q3,q4,q5,q6,q7) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat (in,rs,q1,q2,q3,q4,q5,q6,q7)
	  to ( 1, 2,12,11, 9, 6, 5, 4, 3) ;
	}

part 4025 : default dil14,so14 {
	newattr "$comment" = "Triple 3-Input NOR Gate" ;
	pin (a,b,c,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, y)
	  to ( 3, 4, 5, 6)
	  or (11,12,13,10)
	  or ( 1, 2, 8, 9) ;
	swap (((3,4,5),6), ((11,12,13),10), ((1,2,8),9)) ;
	}

part 4026 : default dil16 {
	newattr "$comment" = "Decade Counter/Divider" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4027 : default dil16 {
	newattr "$comment" = "Dual J-K Master-Slave Flip-Flop" ;
	pin (j,k,c,s,r,q,/q) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( j, k, c,s, r, q,/q)
	  to ( 6, 5, 3,7, 4, 1, 2)
	  or (10,11,13,9,12,15,14) ;
	swap ((6,5,3,7,4,1,2), (10,11,13,9,12,15,14)) ;
	}

part 4028 : default dil16 {
	newattr "$comment" = "BCD-to-Decimal Decoder" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (10,13,12,11, 3,14, 2,15, 1, 6, 7, 4, 9, 5) ;
	}

part 4029 : default dil16 {
	newattr "$comment" = "Presettable Up/Down Counter" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4030 : default dil14,so14 {
	newattr "$comment" = "Quad Exclusive-OR Gate" ;
	pin (a,b,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (13,12,11) ;
	swap (((1,2),3), ((5,6),4), ((8,9),10), ((13,12),11)) ;
	}

part 4031 : default dil16 {
	newattr "$comment" = "64-Stage Static Shift Register" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4032 : mainpart default dil16 {
	newattr "$comment" = "Triple Serial Adder" ;
	pin (a,b,i,s) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( a, b, i, s)
	  to (10,11, 7, 9)
	  or (13,12, 5, 4)
	  or (15,14, 2, 1) ;
	swap ((10,11,7,9), (13,12,5,4), (15,14,2,1)) ;
	}
part 4032s : subpart 4032 {
	pin (3,6) ;
	}

part 4033 : default dil16 {
	newattr "$comment" = "Decade Counter/Divider" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4035 : default dil16 {
	newattr "$comment" = "4-Stage Parallel In/Out Shift Register" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4038 : mainpart default dil16 {
	newattr "$comment" = "Triple Serial Adder" ;
	pin (a,b,i,s) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( a, b, i, s)
	  to (10,11, 7, 9)
	  or (13,12, 5, 4)
	  or (15,14, 2, 1) ;
	swap ((10,11,7,9), (13,12,5,4), (15,14,2,1)) ;
	}
part 4038s : subpart 4038 {
	pin (3,6) ;
	}

part 4040 : default dil16 {
	newattr "$comment" = "12-Stage Binary Ripple Counter" ;
	pin (in,rs,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (in,rs,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12)
	  to (10,11, 9, 7, 6, 5, 3, 2, 4,13,12, 14, 15,  1) ;
	}

part 4041 : default dil14,so14 {
	newattr "$comment" = "Quad True/Complement Buffer" ;
	pin (a,y,/y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, y,/y)
	  to ( 3, 1, 2)
	  or ( 6, 4, 5)
	  or (10, 8, 9)
	  or (13,11,12) ;
	swap ((3,1,2), (6,4,5), (10,8,9), (13,11,12)) ;
	}

part 4042 : mainpart default dil16 {
	newattr "$comment" = "Quad Clocked D Latch" ;
	pin (d,q,/q) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( d, q,/q)
	  to ( 4, 2, 3)
	  or ( 7,10, 9)
	  or (13,11,12)
	  or (14, 1,15) ;
	swap ((4,2,3), (7,10,9), (13,11,12), (14,1,15)) ;
	}
part 4042s : subpart 4042 {
	pin (5,6) ;
	}

part 4043 : mainpart default dil16 {
	newattr "$comment" = "Quad 3-State R-S Latch" ;
	pin (s,r,q) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( s, r, q)
	  to ( 4, 3, 2)
	  or ( 6, 7, 9)
	  or (12,11,10)
	  or (14,15, 1) ;
	swap ((4,3,2), (6,7,9), (12,11,10), (14,15,1)) ;
	}
part 4043s : subpart 4043 {
	pin (5) ;
	}

part 4044 : mainpart default dil16 {
	newattr "$comment" = "Quad 3-State R-S Latch" ;
	pin (r,s,q) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( r, s, q)
	  to ( 4, 3,13)
	  or ( 6, 7, 9)
	  or (12,11,10)
	  or (14,15, 1) ;
	swap ((4,3,13), (6,7,9), (12,11,10), (14,15,1)) ;
	}
part 4044s : subpart 4044 {
	pin (5) ;
	}

part 4045 : default dil14,so14 {
	newattr "$comment" = "21-Stage Counter" ;
	pin (1,16,2,15,8,7,3,14) ;
	}

part 4046 : default dil16 {
	newattr "$comment" = "Micropower Phase-Locked Loop" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4047 : default dil14,so14 {
	newattr "$comment" = "Multivibrator Astable/Monostable" ;
	pin (1,2,3,4,5,6,8,9,10,11,12,13) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	}

part 4049 : default dil16 {
	newattr "$comment" = "Hex Buffer/Converter (inverting)" ;
	pin (a,y) ;
	net "vee" : (1) ;
	net "vss" : (8) ;
	xlat ( a, y)
	  to ( 3, 2)
	  or ( 5, 4)
	  or ( 7, 6)
	  or ( 9,10)
	  or (11,12)
	  or (14,15) ;
	swap ((3,2), (5,4), (7,6), (9,10), (11,12), (14,15)) ;
	}

part 4050 : default dil16 {
	newattr "$comment" = "Hex Buffer/Converter (non-inverting)" ;
	pin (a,y) ;
	net "vee" : (1) ;
	net "vss" : (8) ;
	xlat ( a, y)
	  to ( 3, 2)
	  or ( 5, 4)
	  or ( 7, 6)
	  or ( 9,10)
	  or (11,12)
	  or (14,15) ;
	swap ((3,2), (5,4), (7,6), (9,10), (11,12), (14,15)) ;
	}

part 4051 : default dil16 {
	newattr "$comment" = "8-Channel Multiplexer" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4052 : default dil16 {
	newattr "$comment" = "Differential 4-Channel Multiplexer" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4053 : default dil16 {
	newattr "$comment" = "Triple 2-Input Analog Multiplexer" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4054 : default dil16 {
	newattr "$comment" = "4-Line Liquid Crystal Display Driver" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

part 4060 : default dil16 {
	newattr "$comment" = "14-Stage Counter and Oscillator" ;
	pin (in,rs,o1,o2,q4,q5,q6,q7,q8,q9,q10,q12,q13,q14) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (in,rs,o1,o2,q4,q5,q6,q7,q8,q9,q10,q12,q13,q14)
	  to (11,12, 9,10, 7, 5, 4, 6,14,13, 15,  1,  2,  3) ;
	}

part 4063 : default dil16 {
	newattr "$comment" = "4-Bit Magnitude Comparator" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,c1,c2,c3,x,y,z) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,c1,c2,c3,x,y,z)
	  to (10,12,13,15, 9,11,14, 1, 2, 3, 4,5,6,7) ;
	swap ([ ((10,12,13,15), (9,11,14,1)) ]) ;
	}

part 4066 : default dil14,so14 {
	newattr "$comment" = "Quad Bilateral Switch" ;
	pin (a,b,s) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, s)
	  to ( 1, 2,13)
	  or ( 3, 4, 5)
	  or ( 8, 9, 6)
	  or (10,11,12) ;
	swap (((1,2),13), ((3,4),5), ((8,9),6), ((10,11),12)) ;
	}

part 4068 : default dil14,so14 {
	newattr "$comment" = "8-Input NAND Gate" ;
	pin (a,b,c,d,e,f,g,h,y,/y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat (a,b,c,d, e, f, g,h,y,/y)
	  to (2,3,4,5,12,11,10,9,1,13) ;
	swap ((2),(3),(4),(5),(12),(11),(10),(9)) ;
	}

part 4069 : default dil14,so14 {
	newattr "$comment" = "Hex Inverter" ;
	pin (a,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ((1,2), (3,4), (5,6), (9,8), (11,10), (13,12)) ;
	}

part 4070 : default dil14,so14 {
	newattr "$comment" = "Quad Exclusive-OR Gate" ;
	pin (a,b,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (13,12,11) ;
	swap (((1,2),3), ((5,6),4), ((8,9),10), ((13,12),11)) ;
	}

part 4071 : default dil14,so14 {
	newattr "$comment" = "Quad 2-Input OR Gate" ;
	pin (a,b,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (13,12,11) ;
	swap (((1,2),3), ((5,6),4), ((8,9),10), ((13,12),11)) ;
	}

part 4072 : default dil14,so14 {
	newattr "$comment" = "Dual 4-Input OR Gate" ;
	pin (a,b,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, d, y)
	  to ( 2, 3, 4, 5, 1)
	  or ( 9,10,11,12,13) ;
	swap (((2,3,4,5),1), ((9,10,11,12),13)) ;
	}

part 4073 : default dil14,so14 {
	newattr "$comment" = "Triple 3-Input AND Gate" ;
	pin (a,b,c,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, y)
	  to ( 3, 4, 5, 6)
	  or ( 1, 2, 8, 9)
	  or (11,12,13,10) ;
	swap (((3,4,5),6), ((1,2,8),9), ((11,12,13),10)) ;
	}

part 4075 : default dil14,so14 {
	newattr "$comment" = "Triple 3-Input OR Gate" ;
	pin (a,b,c,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, y)
	  to ( 1, 2, 8, 9)
	  or ( 3, 4, 5, 6)
	  or (11,12,13,10) ;
	swap (((1,2,8),9), ((3,4,5),6), ((11,12,13),10)) ;
	}

part 4081 : default dil14,so14 {
	newattr "$comment" = "Quad 2-Input AND Gate" ;
	pin (a,b,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 6, 5, 4)
	  or ( 8, 9,10)
	  or (13,12,11) ;
	swap (((1,2),3), ((6,5),4), ((8,9),10), ((13,12),11)) ;
	}

part 4082 : default dil14,so14 {
	newattr "$comment" = "Dual 4-Input AND Gate" ;
	pin (a,b,c,d,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, c, d, y)
	  to ( 2, 3, 4, 5, 1)
	  or ( 9,10,11,12,13) ;
	swap (((2,3,4,5),1), ((9,10,11,12),13)) ;
	}

part 4093 : default dil14,so14 {
	newattr "$comment" = "Quad 2-Input NAND Schmitt Trigger" ;
	pin (a,b,y) ;
	net "vee" : (14) ;
	net "vss" : (7) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 6, 5, 4)
	  or ( 8, 9,10)
	  or (13,12,11) ;
	swap (((1,2),3), ((6,5),4), ((8,9),10), ((13,12),11)) ;
	}

part 4098 : default dil16 {
	newattr "$comment" = "Dual Retriggerable Monostable" ;
	pin (a,b, r,q,/q, c,rc) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat ( a, b, r, q,/q, c,rc)
	  to ( 4, 5, 3, 6, 7, 1, 2)
	  or (12,11,13,10, 9,15,14) ;
	swap ((4,5,3,6,7,1,2), (12,11,13,10,9,15,14)) ;
	}

part 4520 : default dil16 {
	newattr "$comment" = "Dual 4-Bit Binary Counter" ;
	pin (clk,en,rs,q1,q2,q3,q4) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	xlat (clk,en,rs,q1,q2,q3,q4)
	  to (  1, 2, 7, 3, 4, 5, 6)
	  or (  9,10,15,11,12,13,14) ;
	swap ((1,2,7,(3,4,5,6)), (9,10,15,(11,12,13,14))) ;
	}

part 45027 : default dil16 {
	newattr "$comment" = "" ;
	pin (1,2,3,4,5,6,7,9,10,11,12,13,14,15) ;
	net "vee" : (16) ;
	net "vss" : (8) ;
	}

/*______________________________________________________________*/
/* Logical Library definition file end */

end.