loglib

/*______________________________________________________________*/
/*								*/
/* LOG Library	: 74ls.def					*/
/* SCM Library	: 74ls.ddb					*/
/*								*/
/* Author	: Bartels System				*/
/* Last Revision: 1997/04/29					*/
/*								*/
/* Copyright (c) 1991-97 Oliver Bartels F+E, Erding		*/
/*______________________________________________________________*/
/*								*/
/* This library provides definitions of				*/
/*								*/
/*	- Bipolar TTL Low Power Schottky / Series 74LS		*/
/*								*/
/* digital integrated circuits logic family.			*/
/*								*/
/* NOTES:							*/
/*								*/
/* Temperature	: 74  = Commercial (0..70 Degree Celcius)	*/
/* Power Supply	: vss = Digital Ground				*/
/*		: vcc = +5V DC					*/
/*								*/
/* The part names used in this library NEITHER do include	*/
/* prefixes referring to the manufacturer NOR do they include	*/
/* suffixes referring to temperature range, timing constraints,	*/
/* package types (as long as pin compatibility is maintained).	*/
/*								*/
/* CONVENTIONS:							*/
/*								*/
/* 1.	The library parts identified by the usual 74ls number	*/
/*	(without manufacturer prefix or package type suffix)	*/
/*	correspond to the entire TTL package or one of several	*/
/*	independent IDENTICAL circuits.				*/
/* 2.	For packages containing two or more independent, but	*/
/*	DIFFERENT circuits several library symbols may be	*/
/*	available, each corresponding to one circuit type.	*/
/*	These library parts are named 74lsNNN (mainpart),	*/
/*	74lsNNNx (subpart), 74lsNNNy (subpart), etc. in the	*/
/*	order of decreasing number of circuits per package and	*/
/*	decreasing complexity.					*/
/* 3.	An effort has been made to make symbols for parts with	*/
/*	similar functions (e.g., gates, bus circuits) as	*/
/*	similar as possible. All pins are placed in a 2mm grid	*/
/*	and the usual distance between adjacent symbol pins is	*/
/*	4mm.							*/
/* 4.	The design of part symbols complies with the following	*/
/*	rules wherever this is not unreasonable:		*/
/*	(a) inputs are on the left, outputs on the right,	*/
/*	(b) control lines are below data or address lines,	*/
/*	(c) data lines are below address lines,			*/
/*	(d) lines corresponding to more significant bits are	*/
/*	    below those corresponding to less significant,	*/
/*	(e) inverting inputs(outputs) are below non-inverting	*/
/*	    lines,						*/
/*	(f) clocks are below set/reset and enable lines		*/
/*______________________________________________________________*/


part 74ls00 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls01 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74ls02 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74ls03 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls04 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74ls05 : default so14,dil14 {
	newattr "$comment" = "Hex Inverter" ;
	newattr "$ttlout" = "OC" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74ls08 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls09 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls10 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74ls11 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74ls12 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74ls13 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74ls14 : default so14,dil14 {
	newattr "$comment" = "Hex Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74ls15 : default so14,dil14 {
	newattr "$comment" = "Triple 3 Input AND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74ls18 : default dil14 {
	newattr "$comment" = "Dual 4 Input NAND Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74ls19 : default so14,dil14 {
	newattr "$comment" = "Hex Schmitt Trigger Inverter" ;
	newattr "$ttlout" = "TP" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 3, 4)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (11,10)
	  or (13,12) ;
	swap ( ( 1, 2), ( 3, 4), ( 5, 6), ( 9, 8), (11,10), (13,12) ) ;
	}

part 74ls20 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74ls21 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input AND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74ls22 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74ls24 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls26 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND, 15V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls27 : default so14,dil14 {
	newattr "$comment" = "Triple 2 Input NOR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, y)
	  to (1, 2,13,12)
	  or (3, 4, 5, 6)
	  or (9,10,11, 8) ;
	swap ( (( 1, 2,13),12), (( 3, 4, 5), 6), (( 9,10,11), 8) ) ;
	}

part 74ls28 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74ls30 : default so14,dil14 {
	newattr "$comment" = "8 Input NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h,y)
	  to (1,2,3,4,5,6,11,12,8) ;
	swap ( (( 1, 2, 3, 4, 5, 6,11,12), 8) ) ;
	}

part 74ls31 : mainpart so16,dil16 {
	newattr "$comment" = "Delay Elements" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,y)
	  to ( 5, 6,7)
	  or (10,11,9) ;
	swap ( (( 5, 6), 7), ((10,11), 9) ) ;
	}

part 74ls31x : subpart 74ls31 {
	pin (a,y) ;
	xlat ( a, y)
	  to ( 3, 4)
	  or (13,12) ;
	swap ( ( 3, 4), (13,12) ) ;
	}

part 74ls31y : subpart 74ls31 {
	pin (a,y) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or (15,14) ;
	swap ( ( 1, 2), (15,14) ) ;
	}

part 74ls32 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls33 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NOR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 2, 3, 1)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (11,12,13) ;
	swap ( (( 2, 3), 1),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((11,12),13) ) ;
	}

part 74ls37 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls38 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input NAND Buffer" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls40 : default so14,dil14 {
	newattr "$comment" = "Dual 4 Input NAND Buffer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c, d,y)
	  to (1, 2, 4, 5,6)
	  or (9,10,12,13,8) ;
	swap ( (( 1, 2, 4, 5), 6), (( 9,10,12,13), 8) ) ;
	}

part 74ls42 : default so16,dil16 {
	newattr "$comment" = "BCD to Decimal Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 74ls47 : default so16,dil16 {
	newattr "$comment" = "BCD to 7-Segment Decoder, 15V Output" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74ls48 : default so16,dil16 {
	newattr "$comment" = "BCD to 7-Segment Decoder/Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74ls49 : default so14,dil14 {
	newattr "$comment" = "BCD to 7-Segment Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (bi,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (bi,a0,a1,a2,a3, a, b,c,d,e, f, g)
	  to ( 3, 5, 1, 2, 4,11,10,9,8,6,13,12) ;
	}

part 74ls51 : mainpart so14,dil14 {
	newattr "$comment" = "3-3/2-2 Input AND-OR-Invert Gates" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a, b, c,d, e, f,y)
	  to (1,12,13,9,10,11,8) ;
	swap ( [  (( 1,12,13)), (( 9,10,11)), 8 ] ) ;
	}

part 74ls51x : subpart 74ls51 {
	pin (a,b,c,d,y) ;
	xlat (a,b,c,d,y)
	  to (2,3,4,5,6) ;
	swap ( [  (( 2, 3)), (( 4, 5)), 6 ] ) ;
	}

part 74ls54 : default so14,dil14 {
	newattr "$comment" = "2-3-3-2 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d,e,f, g, h, i, j,y)
	  to (1,2,3,4,5,9,10,11,12,13,6) ;
	swap internal ( (( 1, 2)), ((12,13)) ) ;
	swap internal ( (( 3, 4, 5)), (( 9,10,11)) ) ;
	}

part 74ls55 : default so14,dil14 {
	newattr "$comment" = "2 Wide 4 Input AND-OR-Invert Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b,c,d, e, f, g, h,y)
	  to (1,2,3,4,10,11,12,13,8) ;
	swap internal ( (( 1, 2, 3, 4)), ((10,11,12,13)) ) ;
	}

part 74ls56 : default dil8 {
	newattr "$comment" = "Frequency Divider 50 to 1" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,clka,clkb,qa,qb,qc) ;
	net "vss" : (4) ;
	net "vcc" : (2) ;
	xlat (clr,clka,clkb,qa,qb,qc)
	  to (  6,   5,   1, 3, 7, 8) ;
	}

part 74ls57 : default dil8 {
	newattr "$comment" = "Frequency Divider 60 to 1" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,clka,clkb,qa,qb,qc) ;
	net "vss" : (4) ;
	net "vcc" : (2) ;
	xlat (clr,clka,clkb,qa,qb,qc)
	  to (  6,   5,   1, 3, 7, 8) ;
	}

part 74ls63 : default so14,dil14 {
	newattr "$comment" = "Hex Current Sensing Interface Gate" ;
	pin (a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, y)
	  to ( 1, 2)
	  or ( 4, 3)
	  or ( 5, 6)
	  or ( 9, 8)
	  or (10,11)
	  or (13,12) ;
	swap ( ( 1, 2), ( 4, 3), ( 5, 6), ( 9, 8), (10,11), (13,12) ) ;
	}

part 74ls68 : default so16,dil16 {
	newattr "$comment" = "Dual 40 MHz Decade Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (1clk1,1qa,/1clr,1clk2,1qb,1qc,1qd,/2clr,2clk,2qa,2qb,2qc,2qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (1clk1,1qa,/1clr,1clk2,1qb,1qc,1qd,/2clr,2clk,2qa,2qb,2qc,2qd)
	  to (    1, 14,    4,   15,  2, 13,  3,   11,   9,  7, 10,  5, 12) ;
	}

part 74ls69 : default dil16 {
	newattr "$comment" = "Dual 40 MHz 4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (1clk1,1qa,/1clr,1clk2,1qb,1qc,1qd,/2clr,2clk,2qa,2qb,2qc,2qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (1clk1,1qa,/1clr,1clk2,1qb,1qc,1qd,/2clr,2clk,2qa,2qb,2qc,2qd)
	  to (    1, 14,    4,   15,  2, 13,  3,   11,   9,  7, 10,  5, 12) ;
	}

part 74ls73 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (j,clk,k,/clr,q,/q) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat ( j,clk, k,/clr, q,/q)
	  to (14,  1, 3,   2,12,13)
	  or ( 7,  5,10,   6, 9, 8) ;
	swap ( (14, 1, 3, 2,12,13), ( 7, 5,10, 6, 9, 8) ) ;
	}

part 74ls74 : default so14,dil14 {
	newattr "$comment" = "Dual D-Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,clk,d,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre,clk, d,/clr,q,/q)
	  to (   4,  3, 2,   1,5, 6)
	  or (  10, 11,12,  13,9, 8) ;
	swap ( ( 4, 3, 2, 1, 5, 6), (10,11,12,13, 9, 8) ) ;
	}

part 74ls75 : default so16,dil16 {
	newattr "$comment" = "Quad Bistable Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (d0,d1,c,q0,/q0,q1,/q1) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (d0,d1, c,q0,/q0,q1,/q1)
	  to ( 2, 3,13,16,  1,15, 14)
	  or ( 6, 7, 4,10, 11, 9,  8) ;
	swap ( ( 2, 3,13,16, 1,15,14), ( 6, 7, 4,10,11, 9, 8) ) ;
	}

part 74ls76 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (j,k,clk,/pre,/clr,q,/q) ;
	net "vss" : (13) ;
	net "vcc" : (5) ;
	xlat (j, k,clk,/pre,/clr, q,/q)
	  to (4,16,  1,   2,   3,15,14)
	  or (9,12,  6,   7,   8,11,10) ;
	swap ( ( 4,16, 1, 2, 3,15,14), ( 9,12, 6, 7, 8,11,10) ) ;
	}

part 74ls77 : default so14,dil14 {
	newattr "$comment" = "4 Bit Bistable Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (c,d0,d1,q0,q1) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat ( c,d0,d1,q0,q1)
	  to (12, 1, 2,14,13)
	  or ( 3, 5, 6, 9, 8) ;
	swap ( (12, 1,14, 2,13), ( 3, 5, 9, 6, 8) ) ;
	}

part 74ls78 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Common Clear/Clock" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/clr,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (11) ;
	net "vcc" : (4) ;
	xlat (clk,/clr,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (  1,   5,    2, 3,14,13, 12,    6,10, 7, 8,  9) ;
	swap internal ( ( 2, 3,14,13,12), ( 6,10, 7, 8, 9) ) ;
	}

part 74ls83 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Full Adder, Fast Carry" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,ci,y0,y1,y2,y3,co) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,ci,y0,y1,y2,y3,co)
	  to (10, 8, 3, 1,11, 7, 4,16,13, 9, 6, 2,15,14) ;
	swap internal ( (10, 8, 3, 1), (11, 7, 4,16) ) ;
	}

part 74ls85 : default so16,dil16 {
	newattr "$comment" = "4 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,b0,b1,b2,b3,"a<b","a=b","a>b","p<q","p=q","p>q")
	  to (10,12,13,15, 9,11,14, 1,    2,    3,    4,    7,    6,    5) ;
	swap internal ( (10,12,13,15, 2, 7), ( 9,11,14, 1, 4, 5) ) ;
	}

part 74ls86 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls90 : default so14,dil14 {
	newattr "$comment" = "Decade Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,r91,r92,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02,r91,r92, a,qa,b,qb,qc,qd)
	  to (  2,  3,  6,  7,14,12,1, 9, 8,11) ;
	swap internal ( (( 2, 3)) ) ;
	swap internal ( (( 6, 7)) ) ;
	}

part 74ls91 : default so14,dil14 {
	newattr "$comment" = "8 Bit Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (ck,a,b,q,/q) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (ck, a, b, q,/q)
	  to ( 9,12,11,13,14) ;
	swap internal ( ((12,11)) ) ;
	}

part 74ls92 : default so14,dil14 {
	newattr "$comment" = "Divide by 12 Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02, a,qa,b,qb,qc,qd)
	  to (  6,  7,14,12,1,11, 9, 8) ;
	swap internal ( (( 6, 7)) ) ;
	}

part 74ls93 : default so14,dil14 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,a,qa,b,qb,qc,qd) ;
	net "vss" : (10) ;
	net "vcc" : (5) ;
	xlat (r01,r02, a,qa,b,qb,qc,qd)
	  to (  2,  3,14,12,1, 9, 8,11) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74ls95 : default so14,dil14 {
	newattr "$comment" = "4 Bit Shift Register PISO" ;
	newattr "$ttlout" = "TP" ;
	pin (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (mode,clk1,clk2,ser,a,qa,b,qb,c,qc,d,qd)
	  to (   6,   9,   8,  1,2,13,3,12,4,11,5,10) ;
	}

part 74ls96 : default so16,dil16 {
	newattr "$comment" = "5 Bit Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,pre,ser,a,qa,b,qb,c,qc,d,qd,e,qe) ;
	net "vss" : (12) ;
	net "vcc" : (5) ;
	xlat (/clr,clk,pre,ser,a,qa,b,qb,c,qc,d,qd,e,qe)
	  to (  16,  1,  8,  9,2,15,3,14,4,13,6,11,7,10) ;
	}

part 74ls107 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (j,clk,k,/clr,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (j,clk, k,/clr,q,/q)
	  to (1, 12, 4,  13,3, 2)
	  or (8,  9,11,  10,5, 6) ;
	swap ( ( 1,12, 4,13, 3, 2), ( 8, 9,11,10, 5, 6) ) ;
	}

part 74ls109 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,/k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk,/k,/clr, q,/q)
	  to (   5, 2,  4, 3,   1, 6, 7)
	  or (  11,14, 12,13,  15,10, 9) ;
	swap ( ( 5, 2, 4, 3, 1, 6, 7), (11,14,12,13,15,10, 9) ) ;
	}

part 74ls112 : default so16,dil16 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,/clr,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/pre, j,clk, k,/clr,q,/q)
	  to (   4, 3,  1, 2,  15,5, 6)
	  or (  10,11, 13,12,  14,9, 7) ;
	swap ( ( 4, 3, 1, 2,15, 5, 6), (10,11,13,12,14, 9, 7) ) ;
	}

part 74ls113 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset" ;
	newattr "$ttlout" = "TP" ;
	pin (/pre,j,clk,k,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/pre, j,clk, k,q,/q)
	  to (   4, 3,  1, 2,5, 6)
	  or (  10,11, 13,12,9, 8) ;
	swap ( ( 4, 3, 1, 2, 5, 6), (10,11,13,12, 9, 8) ) ;
	}

part 74ls114 : default so14,dil14 {
	newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,/1pre,1j,1k,1q,/1q,/2pre,2j,2k,2q,/2q)
	  to (   1, 13,    4, 3, 2, 5,  6,   10,11,12, 9,  8) ;
	swap ( [  1,13, ( 4, 3, 2, 5, 6), (10,11,12, 9, 8) ] ) ;
	}

part 74ls122 : default so14,dil14 {
	newattr "$comment" = "Monostable Multivibrator, Retriggerable" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,b1,b2,/clr,ri,cx,rxcx,q,/q) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a1,a2,b1,b2,/clr,ri,cx,rxcx,q,/q)
	  to ( 1, 2, 3, 4,   5, 9,11,  13,8, 6) ;
	swap internal ( (( 1, 2)) ) ;
	swap internal ( (( 3, 4)) ) ;
	}

part 74ls123 : default so16,dil16 {
	newattr "$comment" = "Dual Monostable Multivibrator, Retrigg." ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/clr,cx,rx,q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,rx, q,/q)
	  to (1, 2,   3,14,15,13, 4)
	  or (9,10,  11, 6, 7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 74ls125 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 74ls126 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Buffer Gate" ;
	newattr "$ttlout" = "TS" ;
	pin (c,a,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( c, a, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or (10, 9, 8)
	  or (13,12,11) ;
	swap ( ( 1, 2, 3), ( 4, 5, 6), (10, 9, 8), (13,12,11) ) ;
	}

part 74ls132 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Schmitt Trigger" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls133 : default so16,dil16 {
	newattr "$comment" = "13 Input Positive NAND Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,j,k,l,m,y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,d,e,f,g, h, i, j, k, l, m,y)
	  to (1,2,3,4,5,6,7,10,11,12,13,14,15,9) ;
	swap ( (( 1, 2, 3, 4, 5, 6, 7,10,11,12,13,14,15), 9) ) ;
	}

part 74ls136 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 4, 5, 6)
	  or ( 9,10, 8)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 4, 5), 6),
	       (( 9,10), 8),
	       ((12,13),11) ) ;
	}

part 74ls137 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder, Address Registers" ;
	newattr "$ttlout" = "TP" ;
	pin (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/gl,a,b,c,g1,/g2,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (  4,1,2,3, 6,  5,15,14,13,12,11,10, 9, 7) ;
	}

part 74ls138 : default so16,dil16 {
	newattr "$comment" = "3 of 8 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b,c,g1,/g2a,/g2b,y0,y1,y2,y3,y4,y5,y6,y7)
	  to (1,2,3, 6,   4,   5,15,14,13,12,11,10, 9, 7) ;
	swap internal ( (( 4, 5)) ) ;
	}

part 74ls139 : default so16,dil16 {
	newattr "$comment" = "Dual 2 of 4 Decoder" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/g,y0,y1,y2,y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a, b,/g,y0,y1,y2,y3)
	  to ( 2, 3, 1, 4, 5, 6, 7)
	  or (14,13,15,12,11,10, 9) ;
	swap ( ( 2, 3, 1, 4, 5, 6, 7), (14,13,15,12,11,10, 9) ) ;
	}

part 74ls145 : default so16,dil16 {
	newattr "$comment" = "BCD to Decimal Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,a2,a3,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9)
	  to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ;
	}

part 74ls147 : default so16,dil16 {
	newattr "$comment" = "10-Decimal to 4-BCD Priority Encoder" ;
	newattr "$ttlout" = "TP" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,i9,a,b,c,d) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,i9,a,b,c, d)
	  to (11,12,13, 1, 2, 3, 4, 5,10,9,7,6,14) ;
	}

part 74ls148 : default so16,dil16 {
	newattr "$comment" = "8 to 3 Octal Priority Encoder" ;
	newattr "$ttlout" = "TP" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2)
	  to (10,11,12,13, 1, 2, 3, 4, 5,15,14, 9, 7, 6) ;
	}

part 74ls151 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74ls152 : default so14,dil14 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	pin (d0,d1,d2,d3,d4,d5,d6,d7,a,b,c,w) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (d0,d1,d2,d3,d4,d5,d6,d7, a,b,c,w)
	  to ( 5, 4, 3, 2, 1,13,12,11,10,9,8,6) ;
	}

part 74ls153 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74ls155 : default so16,dil16 {
	newattr "$comment" = "Dual 1 of 4 Decoder/Demultiplexer" ;
	newattr "$ttlout" = "TP" ;
	pin (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3)
	  to (13, 3,  2, 1,  7,  6,  5,  4, 14, 15,  9, 10, 11, 12) ;
	}

part 74ls156 : default so16,dil16 {
	newattr "$comment" = "Dual 1 of 4 Decoder/Demultiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a0,a1,/g1,c1,1y0,1y1,1y2,1y3,/g2,/c2,2y0,2y1,2y2,2y3)
	  to (13, 3,  2, 1,  7,  6,  5,  4, 14, 15,  9, 10, 11, 12) ;
	}

part 74ls157 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74ls158 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,sel,1a,1b,y1,2a,2b,y2,3a,3b,y3,4a,4b,y4)
	  to (15,  1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74ls160 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74ls161 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Direct Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74ls162 : default so16,dil16 {
	newattr "$comment" = "BCD Decade Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74ls163 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Counter, Sync. Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,/load,ent,enp,clk,rco,a,qa,b,qb,c,qc,d,qd)
	  to (   1,    9, 10,  7,  2, 15,3,14,4,13,5,12,6,11) ;
	}

part 74ls164 : default so14,dil14 {
	newattr "$comment" = "8 Bit Shift Register SIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/clr,clk,a,b,qa,qb,qc,qd,qe,qf,qg,qh)
	  to (   9,  8,1,2, 3, 4, 5, 6,10,11,12,13) ;
	swap internal ( (( 1, 2)) ) ;
	}

part 74ls165 : default so16,dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh,/qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (shld,clkinh,clk,ser, a, b, c, d,e,f,g,h,qh,/qh)
	  to (   1,    15,  2, 10,11,12,13,14,3,4,5,6, 9,  7) ;
	}

part 74ls166 : default so16,dil16 {
	newattr "$comment" = "8 Bit PISO Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clkinh,clk,ser,a,b,c,d,e,f,g,h,qh) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clkinh,clk,ser,a,b,c,d, e, f, g, h,qh)
	  to (   9,  15,     6,  7,  1,2,3,4,5,10,11,12,14,13) ;
	}

part 74ls168 : default dil16 {
	newattr "$comment" = "4 Bit Decade Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74ls169 : default so16,dil16 {
	newattr "$comment" = "4 Bit Binary Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74ls170 : default so16,dil16 {
	newattr "$comment" = "4 by 4 Register File" ;
	newattr "$ttlout" = "TP" ;
	pin (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to ( 5, 4,14,13, 12, 11,15,10, 1, 9, 2, 7, 3, 6) ;
	}

part 74ls171 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop, Clear" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (  13, 12,14,15,  1, 4, 3,  2, 5, 6,  7,11,10,  9) ;
	swap ( [ 13,12,
	       (14,15, 1),
	       ( 4, 3, 2),
	       ( 5, 6, 7),
	       (11,10, 9) ] ) ;
	}

part 74ls173 : default so16,dil16 {
	newattr "$comment" = "Quad D Register" ;
	newattr "$ttlout" = "TS" ;
	pin (clr,m,n,/g1,/g2,clk,1d,1q,2d,2q,3d,3q,4d,4q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,m,n,/g1,/g2,clk,1d,1q,2d,2q,3d,3q,4d,4q)
	  to ( 15,1,2,  9, 10,  7,14, 3,13, 4,12, 5,11, 6) ;
	swap internal ( (( 1, 2)) ) ;
	swap internal ( (( 9,10)) ) ;
	}

part 74ls174 : default so16,dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,d2,q2,d3,d4,q3,q4,d5,q5,d6,q6) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,d2,q2,d3,q3,d4,q4,d5,q5,d6,q6)
	  to (   1,  9, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  1, 9,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 74ls175 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk,d1,q1,/q1,d2,q2,/q2,d3,q3,/q3,d4,q4,/q4)
	  to (   1,  9, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  1, 9,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 74ls181 : default so24,dil24,dil24b {
	newattr "$comment" = "4 Bit ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	     /a2,/b2,/f2,/a3,/b3,/f3) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (s0,s1,s2,s3,m,cn,/p,/g,"a=b","cn+4",/a0,/b0,/f0,/a1,/b1,/f1,
	      /a2,/b2,/f2,/a3,/b3,/f3)
	  to ( 6, 5, 4, 3,8, 7,15,17,   14,    16,  2,  1,  9, 23, 22, 10,
	       21, 20, 11, 19, 18, 13) ;
	}

part 74ls183 : default so14,dil14 {
	newattr "$comment" = "Dual Carry Save Full Adder" ;
	newattr "$ttlout" = "TP" ;
	pin (ci,a,b,co,s) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (ci, a, b,co,s)
	  to ( 4, 1, 3, 5,6)
	  or (11,13,12,10,8) ;
	swap ( (( 1, 3), 4, 5, 6), ((13,12),11,10, 8) ) ;
	}

part 74ls190 : default so16,dil16 {
	newattr "$comment" = "Synchronous Up/Down BCD Counter" ;
	newattr "$ttlout" = "OC" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74ls191 : default so16,dil16 {
	newattr "$comment" = "Synchronous Up/Down Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/cten,du,clk,/load,maxmin,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/cten,du,clk,/load,maxmin,/rco, a,qa,b,qb, c,qc,d,qd)
	  to (    4, 5, 14,   11,    12,  13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74ls192 : default so16,dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock BCD Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74ls193 : default so16,dil16 {
	newattr "$comment" = "Sync. Up/Down Dual Clock Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (clr,up,down,/load,/co,/bo,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clr,up,down,/load,/co,/bo, a,qa,b,qb, c,qc,d,qd)
	  to ( 14, 5,   4,   11, 12, 13,15, 3,1, 2,10, 6,9, 7) ;
	}

part 74ls194 : default so16,dil16 {
	newattr "$comment" = "4 Bit Universal Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,s0,s1,clk,srser,a,qa,b,qb,c,qc,d,slser,qd)
	  to (   1, 9,10, 11,    2,3,15,4,14,5,13,6,    7,12) ;
	}

part 74ls195 : default so16,dil16 {
	newattr "$comment" = "4 Bit Shift Register PIPO" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,shld,clk,j,/k,a,qa,b,qb,c,qc,d,qd,/qd)
	  to (   1,   9, 10,2, 3,4,15,5,14,6,13,7,12, 11) ;
	}

part 74ls196 : default so14,dil14 {
	newattr "$comment" = "Presetable Decade (Bi-Quinary) Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/ld,/clr,clk1,a,qa,clk2,b,c,d,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/ld,/clr,clk1,a,qa,clk2, b,c, d,qb,qc,qd)
	  to (  1,  13,   8,4, 5,   6,10,3,11, 9, 2,12) ;
	}

part 74ls197 : default so14,dil14 {
	newattr "$comment" = "Presetable 4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/ld,/clr,clk1,a,qa,clk2,b,c,d,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (/ld,/clr,clk1,a,qa,clk2, b,c, d,qb,qc,qd)
	  to (  1,  13,   8,4, 5,   6,10,3,11, 9, 2,12) ;
	}

part 74ls221 : default so16,dil16 {
	newattr "$comment" = "Dual Monostable Multivibr., Schm.Trigger" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/clr,cx,"rx/cx",q,/q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a, b,/clr,cx,"rx/cx", q,/q)
	  to (1, 2,   3,14,     15,13, 4)
	  or (9,10,  11, 6,      7, 5,12) ;
	swap ( ( 1, 2, 3,14,15,13, 4), ( 9,10,11, 6, 7, 5,12) ) ;
	}

part 74ls222 : default dil20 {
	newattr "$comment" = "Asynchronous FIFO Memory 16x4 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (oe,/clr,ldck,ire,unck,ore,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (oe,/clr,ldck,ire,unck,ore,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,  11,   4,  2,  19, 18, 3,  17, 5,16, 7,14, 8,13, 9,12) ;
	swap internal ( ( 5,16), ( 7,14), ( 8,13), ( 9,12) ) ;
	}

part 74ls224 : default so16,dil16 {
	newattr "$comment" = "Asynchronous FIFO Memory 16x4 Bit" ;
	newattr "$ttlout" = "TS" ;
	pin (oe,/clr,ldck,unck,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (oe,/clr,ldck,unck,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,   9,   3,  15, 2,  14, 4,13, 5,12, 6,11, 7,10) ;
	swap internal ( ( 4,13), ( 5,12), ( 6,11), ( 7,10) ) ;
	}

part 74ls227 : default so20,dil20 {
	newattr "$comment" = "Asynchronous FIFO Memory 16x4 Bit" ;
	newattr "$ttlout" = "OC" ;
	pin (oe,/clr,ldck,ire,unck,ore,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (oe,/clr,ldck,ire,unck,ore,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,  11,   4,  2,  19, 18, 3,  17, 5,16, 7,14, 8,13, 9,12) ;
	swap internal ( ( 5,16), ( 7,14), ( 8,13), ( 9,12) ) ;
	}

part 74ls228 : default so16 {
	newattr "$comment" = "Asynchronous FIFO Memory 16x4 Bit" ;
	newattr "$ttlout" = "OC" ;
	pin (oe,/clr,ldck,unck,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (oe,/clr,ldck,unck,ir,"or",d0,q0,d1,q1,d2,q2,d3,q3)
	  to ( 1,   9,   3,  15, 2,  14, 4,13, 5,12, 6,11, 7,10) ;
	swap internal ( ( 4,13), ( 5,12), ( 6,11), ( 7,10) ) ;
	}

part 74ls240 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74ls241 : default so20,dil20 {
	newattr "$comment" = "Octal Buffer/Line Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4,2g,2a1,2y1,2a2,2y2,2a3,2y3,
	     2a4,2y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/1g,1a1,1y1,1a2,1y2,1a3,1y3,1a4,1y4)
	  to (  1,  2, 18,  4, 16,  6, 14,  8, 12) ;
	xlat (2g,2a1,2y1,2a2,2y2,2a3,2y3,2a4,2y4)
	  to (19, 11,  9, 13,  7, 15,  5, 17,  3) ;
	swap internal ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ] ) ;
	swap internal ( [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74ls242 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74ls243 : default so14,dil14 {
	newattr "$comment" = "Quad Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (gba,/gab,a1,b1,a2,b2,a3,b3,a4,b4)
	  to ( 13,   1, 3,11, 4,10, 5, 9, 6, 8) ;
	swap ( [ 13, 1, ( 3,11), ( 4,10), ( 5, 9), ( 6, 8) ] ) ;
	}

part 74ls244 : default so20,dil20 {
	newattr "$comment" = "Octal Driver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a1,y1,a2,y2,a3,y3,a4,y4) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,a1,y1,a2,y2,a3,y3,a4,y4)
	  to ( 1, 2,18, 4,16, 6,14, 8,12)
	  or (19,11, 9,13, 7,15, 5,17, 3) ;
	swap ( [  1, ( 2,18), ( 4,16), ( 6,14), ( 8,12) ],
	       [ 19, (11, 9), (13, 7), (15, 5), (17, 3) ] ) ;
	}

part 74ls245 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls246 : default so16,dil16 {
	newattr "$comment" = "BCD to 7 Segment Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74ls247 : default so16,dil16 {
	newattr "$comment" = "BCD to 7 Segment Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74ls248 : default so16,dil16 {
	newattr "$comment" = "BCD to 7 Segment Decoder/Driver" ;
	newattr "$ttlout" = "TP" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74ls249 : default so16,dil16 {
	newattr "$comment" = "BCD to 7 Segment Decoder/Driver" ;
	newattr "$ttlout" = "OC" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74ls251 : default so16,dil16 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,a,b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g, a, b,c,d0,d1,d2,d3,d4,d5,d6,d7,y,w)
	  to ( 7,11,10,9, 4, 3, 2, 1,15,14,13,12,5,6) ;
	}

part 74ls253 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74ls257 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74ls258 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,ab,1a,1b,1y,2a,2b,2y,3a,3b,3y,4a,4b,4y)
	  to (15, 1, 2, 3, 4, 5, 6, 7,11,10, 9,14,13,12) ;
	swap ( [ 15, 1,
	       ( 2, 3, 4),
	       ( 5, 6, 7),
	       (11,10, 9),
	       (14,13,12) ] ) ;
	}

part 74ls259 : default so16,dil16 {
	newattr "$comment" = "8 Bit Addressable Set-Reset Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,/g,d,/clr,q0,q1,q2,q3,q4,q5,q6,q7) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (s0,s1,s2,/g, d,/clr,q0,q1,q2,q3,q4,q5,q6,q7)
	  to ( 1, 2, 3,14,13,  15, 4, 5, 6, 7, 9,10,11,12) ;
	}

part 74ls261 : default so16,dil16 {
	newattr "$comment" = "4 by 2 Bit Parallel Binary Multiplier" ;
	newattr "$ttlout" = "TP" ;
	pin (b0,b1,b2,b3,b4,m0,m1,m2,g,q0,q1,q2,q3,/q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (b0,b1,b2,b3,b4,m0,m1,m2,g,q0,q1,q2,q3,/q4)
	  to (13,14,15, 1, 2,11,12, 4,3,10, 9, 7, 6,  5) ;
	}

part 74ls266 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive NOR Gate" ;
	newattr "$ttlout" = "OC" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((12,13),11) ) ;
	}

part 74ls273 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (   1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74ls279 : mainpart dil16 {
	newattr "$comment" = "Quad Set-Reset Latches" ;
	newattr "$ttlout" = "TP" ;
	pin (s1,s2,r,q) ;
	net "vcc" : (16) ;
	net "vss" : (8) ;
	xlat (s1,s2, r,q)
	  to ( 2, 3, 1,4)
	  or (11,12,10,9) ;
	swap ( (( 2, 3), 1, 4), ((11,12),10, 9) ) ;
	}

part 74ls279x : subpart 74ls279 {
	pin (s,r,q) ;
	xlat ( s, r, q)
	  to ( 6, 5, 7)
	  or (15,14,13) ;
	swap ( ( 6, 5, 7), (15,14,13) ) ;
	}

part 74ls280 : default so14,dil14 {
	newattr "$comment" = "9 Bit Odd/Even Parity Generator/Checker" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,e,f,g,h,i,even,odd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (a,b, c, d, e, f,g,h,i,even,odd)
	  to (8,9,10,11,12,13,1,2,4,   5,  6) ;
	swap ( (( 8, 9,10,11,12,13, 1, 2, 4), 5, 6) ) ;
	}

part 74ls283 : default so16,dil16 {
	newattr "$comment" = "4 Bit Full Adder, Fast Carry" ;
	newattr "$ttlout" = "TP" ;
	pin (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a1,a2,a3,a4,b1,b2,b3,b4,c0,s1,s2,s3,s4,c4)
	  to ( 5, 3,14,12, 6, 2,15,11, 7, 4, 1,13,10, 9) ;
	swap internal ( (( 5, 6),( 3, 2),(14,15),(12,11)) ) ;
	}

part 74ls290 : default so14,dil14 {
	newattr "$comment" = "Decade Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,r91,r92,a,qa,b,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (r01,r02,r91,r92, a,qa, b,qb,qc,qd)
	  to ( 12, 13,  1,  3,10, 9,11, 5, 4, 8) ;
	swap internal ( ((12,13)) ) ;
	swap internal ( (( 1, 3)) ) ;
	}

part 74ls292 : default dil16 {
	newattr "$comment" = "30 Bit Programmable Frequency Divider" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk1,clk2,a,b,c,d,e,tp1,tp2,tp3,q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk1,clk2, a,b, c, d,e,tp1,tp2,tp3,q)
	  to (  11,   4,   5,10,1,15,14,2,  3,  6, 13,7) ;
	}

part 74ls293 : default so14,dil14 {
	newattr "$comment" = "4 Bit Binary Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (r01,r02,a,qa,b,qb,qc,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (r01,r02, a,qa, b,qb,qc,qd)
	  to ( 12, 13,10, 9,11, 5, 4, 8) ;
	swap internal ( ((12,13)) ) ;
	}

part 74ls294 : default dil16 {
	newattr "$comment" = "4 Bit Binary Counter Frequency Divider" ;
	newattr "$ttlout" = "TP" ;
	pin (/clr,clk1,clk2,a,b,c,d,tp,q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/clr,clk1,clk2,a,b, c, d,tp,q)
	  to (  11,   4,   5,2,1,15,14, 3,7) ;
	}

part 74ls295 : default so14,dil14 {
	newattr "$comment" = "4 Bit Shift Register" ;
	newattr "$ttlout" = "TP" ;
	pin (oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat (oc,ldsh,clk,ser,a,qa,b,qb,c,qc,d,qd)
	  to ( 8,   6,  9,  1,2,13,3,12,4,11,5,10) ;
	}

part 74ls297 : default dil16 {
	newattr "$comment" = "Digital Phase Locked Loop" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,c,d,kclk,du,enctr,idclk,pa1,pb,pa2,idout,xorpd,ecpd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (a,b, c, d,kclk,du,enctr,idclk,pa1,pb,pa2,idout,xorpd,ecpd)
	  to (2,1,15,14,   4, 6,    3,    5,  9,10, 13,    7,   11,  12) ;
	}

part 74ls298 : default so16,dil16 {
	newattr "$comment" = "Quad 2 to 1 Multiplexer, Storage" ;
	newattr "$ttlout" = "TP" ;
	pin (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ws,clk,a1,a2,qa,b1,b2,qb,c1,c2,qc,d1,d2,qd)
	  to (10, 11, 3, 2,15, 4, 1,14, 9, 5,13, 7, 6,12) ;
	swap ( [ 10,11,
	       ( 3, 2,15),
	       ( 4, 1,14),
	       ( 9, 5,13),
	       ( 7, 6,12) ] ) ;
	}

part 74ls299 : default so20,dil20 {
	newattr "$comment" = "8 Bit Universal PIPO Shift Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74ls320 : default dil16 {
	newattr "$comment" = "Crystal Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (tank1,tank2,xtal1,xtal2,"vcc'",ffd,f,/f,"f'","/f'",ffq) ;
	net "vss" : (3,8) ;
	net "vcc" : (16) ;
	xlat (tank1,tank2,xtal1,xtal2,"vcc'",ffd,f,/f,"f'","/f'",ffq)
	  to (    1,    2,   14,   15,    11,  5,7,12,  10,    9,  4) ;
	}

part 74ls321 : default dil16 {
	newattr "$comment" = "Crystal Controlled Oscillator" ;
	newattr "$ttlout" = "TP" ;
	pin (tank1,tank2,xtal1,xtal2,"vcc'",ffd,f,/f,"f'","/f'","f/2","f/4",
	     ffq) ;
	net "vss" : (3,8) ;
	net "vcc" : (16) ;
	xlat (tank1,tank2,xtal1,xtal2,"vcc'",ffd,f,/f,"f'","/f'","f/2","f/4",
	      ffq)
	  to (    1,    2,   14,   15,    11,  5,7,12,  10,    9,   13,    6,
	        4) ;
	}

part 74ls322 : default so20,dil20 {
	newattr "$comment" = "8 Bit Shift Register, Sign Extend" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/oe,/g,"s/p",clk,/se,ds,d0,d1,"a/qa","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh","qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/oe,/g,"s/p",clk,/se,ds,d0,d1,"a/qa","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh","qh'")
	  to (   9,  8, 1,    2, 11, 18,19, 3,17,     4,    16,     5,    15,
	           6,    14,     7,    13,   12) ;
	}

part 74ls323 : default so20,dil20 {
	newattr "$comment" = "8 Bit Shift/Storage Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	     "e/qe","f/qf","g/qg","h/qh",sl,"qh'") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/clr,/g1,/g2,s0,s1,clk,sr,"a/qa","qa'","b/qb","c/qc","d/qd",
	      "e/qe","f/qf","g/qg","h/qh",sl,"qh'")
	  to (   9,  2,  3, 1,19, 12,11,     7,    8,    13,     6,    14,
	           5,    15,     4,    16,18,   17) ;
	swap internal ( (( 2, 3)) ) ;
	}

part 74ls347 : default so16,dil16 {
	newattr "$comment" = "LS47 with 7 Volt Output" ;
	pin (bo,bi,lt,a0,a1,a2,a3,a,b,c,d,e,f,g) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (bo,bi,lt,a0,a1,a2,a3, a, b, c, d,e, f, g)
	  to ( 4, 5, 3, 7, 1, 2, 6,13,12,11,10,9,15,14) ;
	}

part 74ls348 : default so16,dil16 {
	newattr "$comment" = "8 to 3 Line Priority Encoder" ;
	newattr "$ttlout" = "TS" ;
	pin (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (i1,i2,i3,i4,i5,i6,i7,i8,ei,eo,gs,a0,a1,a2)
	  to (10,11,12,13, 1, 2, 3, 4, 5,15,14, 9, 7, 6) ;
	}

part 74ls352 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74ls353 : default so16,dil16 {
	newattr "$comment" = "Dual 4 to 1 Data Selector/MUX" ;
	newattr "$ttlout" = "TS" ;
	pin (a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( a,b,/1g,1c0,1c1,1c2,1c3,1y,/2g,2c0,2c1,2c2,2c3,2y)
	  to (14,2,  1,  6,  5,  4,  3, 7, 15, 10, 11, 12, 13, 9) ;
	swap ( [ 14, 2, ( 1, 6, 5, 4, 3, 7), (15,10,11,12,13, 9) ] ) ;
	}

part 74ls354 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74ls355 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,/dc,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74ls356 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "TS" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74ls357 : default so20,dil20 {
	newattr "$comment" = "8 to 1 Data Selector/Multiplexer" ;
	newattr "$ttlout" = "OC" ;
	pin (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7,y,w) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g1,/g2,g3,/sc,s0,s1,s2,clk,d0,d1,d2,d3,d4,d5,d6,d7, y, w)
	  to ( 15, 16,17, 11,14,13,12,  9, 8, 7, 6, 5, 4, 3, 2, 1,19,18) ;
	swap internal ( ((15,16)) ) ;
	}

part 74ls373 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc, c,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1,11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74ls374 : default so20,dil20 {
	newattr "$comment" = "Octal D-Type Transparent Latch and FF" ;
	newattr "$ttlout" = "TS" ;
	pin (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/oc,clk,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to (  1, 11, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [  1,11,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74ls375 : default so16,dil16 {
	newattr "$comment" = "Quad Bistable Latch" ;
	newattr "$ttlout" = "TP" ;
	pin (1d,c,1q,/1q,2d,2q,/2q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat ( c,1d,1q,/1q,2d,2q,/2q)
	  to ( 4, 1, 3,  2, 7, 5,  6)
	  or (12, 9,11, 10,15,13, 14) ;
	swap ( [  4, ( 1, 3, 2), ( 7, 5, 6) ],
	       [ 12, ( 9,11,10), (15,13,14) ] ) ;
	}

part 74ls377 : default so20,dil20 {
	newattr "$comment" = "Octal D-Flip-Flop with Data Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q,7d,7q,8d,8q)
	  to ( 11, 1, 3, 2, 4, 5, 7, 6, 8, 9,13,12,14,15,17,16,18,19) ;
	swap ( [ 11, 1,
	       ( 3, 2),
	       ( 4, 5),
	       ( 7, 6),
	       ( 8, 9),
	       (13,12),
	       (14,15),
	       (17,16),
	       (18,19) ] ) ;
	}

part 74ls378 : default so16,dil16 {
	newattr "$comment" = "Hex D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,/g,1d,1q,2d,2q,3d,3q,4d,4q,5d,5q,6d,6q)
	  to (  9, 1, 3, 2, 4, 5, 6, 7,11,10,13,12,14,15) ;
	swap ( [  9, 1,
	       ( 3, 2),
	       ( 4, 5),
	       ( 6, 7),
	       (11,10),
	       (13,12),
	       (14,15) ] ) ;
	}

part 74ls379 : default so16,dil16 {
	newattr "$comment" = "Quad D-Flip-Flop" ;
	newattr "$ttlout" = "TP" ;
	pin (clk,/g,1d,1q,/1q,2d,2q,/2q,3d,3q,/3q,4d,4q,/4q) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (clk,/g,1d,1q,/1q,2d,2q,/2q,3d,3q,/3q,4d,4q,/4q)
	  to (  9, 1, 4, 2,  3, 5, 7,  6,12,10, 11,13,15, 14) ;
	swap ( [  9, 1,
	       ( 4, 2, 3),
	       ( 5, 7, 6),
	       (12,10,11),
	       (13,15,14) ] ) ;
	}

part 74ls381 : default so20,dil20 {
	newattr "$comment" = "ALU/Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,cn,/p,/g,a0,b0,f0,a1,b1,f1,a2,b2,f2,a3,b3,f3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,s2,cn,/p,/g,a0,b0,f0,a1,b1,f1,a2,b2,f2,a3,b3,f3)
	  to ( 5, 6, 7,15,14,13, 3, 4, 8, 1, 2, 9,19,18,11,17,16,12) ;
	}

part 74ls382 : default so20,dil20 {
	newattr "$comment" = "4 Bit Arithemetic Function Generator" ;
	newattr "$ttlout" = "TP" ;
	pin (s0,s1,s2,cn,a0,b0,f0,a1,b1,f1,a2,b2,a3,b3,f2,ovr,"cn+4",f3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (s0,s1,s2,cn,a0,b0,f0,a1,b1,f1,a2,b2,a3,b3,f2,ovr,"cn+4",f3)
	  to ( 5, 6, 7,15, 3, 4, 8, 1, 2, 9,19,18,17,16,11, 13,    14,12) ;
	}

part 74ls386 : default so14,dil14 {
	newattr "$comment" = "Quad 2 Input Exclusive OR Gate" ;
	newattr "$ttlout" = "TP" ;
	pin (a,b,y) ;
	net "vss" : (7) ;
	net "vcc" : (14) ;
	xlat ( a, b, y)
	  to ( 1, 2, 3)
	  or ( 5, 6, 4)
	  or ( 8, 9,10)
	  or (12,13,11) ;
	swap ( (( 1, 2), 3),
	       (( 5, 6), 4),
	       (( 8, 9),10),
	       ((12,13),11) ) ;
	}

part 74ls595 : default so16,dil16 {
	newattr "$comment" = "8 Bit Shift Register, Output Register" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'") ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/g,rck,/sclr,sck,ser,qa,qb,qc,qd,qe,qf,qg,qh,"qh'")
	  to (13, 12,   10, 11, 14,15, 1, 2, 3, 4, 5, 6, 7,    9) ;
	}

part 74ls638 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls639 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls640 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls641 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls642 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls643 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver true inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls644 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls645 : default so20,dil20 {
	newattr "$comment" = "Octal Bus Transceiver noninverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,dir,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,a8,b8)
	  to (19,  1, 2,18, 3,17, 4,16, 5,15, 6,14, 7,13, 8,12, 9,11) ;
	swap ( [ 19, 1,
	       ( 2,18),
	       ( 3,17),
	       ( 4,16),
	       ( 5,15),
	       ( 6,14),
	       ( 7,13),
	       ( 8,12),
	       ( 9,11) ] ) ;
	}

part 74ls646 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74ls647 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74ls648 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74ls649 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,
	     b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g,dir,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74ls651 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74ls652 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register" ;
	newattr "$ttlout" = "TS" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74ls653 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74ls654 : default so24,dil24,dil24b {
	newattr "$comment" = "Octal Bus Transceiver/Register inverting" ;
	newattr "$ttlout" = "TSOC" ;
	pin (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	     a7,b7,a8,b8) ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/gba,gab,cba,sba,cab,sab,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,
	      a7,b7,a8,b8)
	  to (  21,  3, 23, 22,  1,  2, 4,20, 5,19, 6,18, 7,17, 8,16, 9,15,
	      10,14,11,13) ;
	swap ( [ 21, 3,23,22, 1, 2,
	       ( 4,20),
	       ( 5,19),
	       ( 6,18),
	       ( 7,17),
	       ( 8,16),
	       ( 9,15),
	       (10,14),
	       (11,13) ] ) ;
	}

part 74ls668 : default so16,dil16 {
	newattr "$comment" = "Synchronous 4 Bit Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74ls669 : default so16,dil16 {
	newattr "$comment" = "Synchronous 4 Bit Up/Down Counter" ;
	newattr "$ttlout" = "TP" ;
	pin (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (/load,ud,/ent,/enp,clk,/rco,a,qa,b,qb,c,qc,d,qd)
	  to (    9, 1,  10,   7,  2,  15,3,14,4,13,5,12,6,11) ;
	}

part 74ls670 : default so16,dil16 {
	newattr "$comment" = "4 by 4 Register File" ;
	newattr "$ttlout" = "TS" ;
	pin (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4) ;
	net "vss" : (8) ;
	net "vcc" : (16) ;
	xlat (ra,rb,wa,wb,/gw,/gr,d1,q1,d2,q2,d3,q3,d4,q4)
	  to ( 5, 4,14,13, 12, 11,15,10, 1, 9, 2, 7, 3, 6) ;
	}

part 74ls671 : default so20,dil20 {
	newattr "$comment" = "4 Bit Univ. Shift Register/Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/s",rck,/sclr,s0,s1,sck,casc,srser,a,qa,b,qb,c,qc,d,slser,
	     qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/s",rck,/sclr,s0,s1,sck,casc,srser,a,qa,b,qb,c,qc,d,slser,
	      qd)
	  to (12,   11,  9,    8,14,13,  2,  19,    1,3,18,4,17,5,16,6,    7,
	      15) ;
	}

part 74ls672 : default so20,dil20 {
	newattr "$comment" = "4 Bit Univ. Shift Register/Latch" ;
	newattr "$ttlout" = "TS" ;
	pin (/g,"r/s",rck,/sclr,s0,s1,sck,casc,srser,a,qa,b,qb,c,qc,d,slser,
	     qd) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,"r/s",rck,/sclr,s0,s1,sck,casc,srser,a,qa,b,qb,c,qc,d,slser,
	      qd)
	  to (12,   11,  9,    8,14,13,  2,  19,    1,3,18,4,17,5,16,6,    7,
	      15) ;
	}

part 74ls681 : default so20,dil20 {
	newattr "$comment" = "4 Bit Parallel Binary Accumulator" ;
	newattr "$ttlout" = "TP" ;
	pin (as0,as1,as2,m,cn,rs0,rs1,rs2,clk,/p,/g,"cn+4","ri/lo","li/ro",
	     io0,io1,io2,io3) ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (as0,as1,as2, m,cn,rs0,rs1,rs2,clk,/p,/g,"cn+4","ri/lo","li/ro",
	      io0,io1,io2,io3)
	  to ( 18, 17, 16,15, 6,  4,  3,  2,  1, 9, 7,     8,     19,      5,
	       14, 13, 12, 11) ;
	}

part 74ls682 : default so20,dil20 {
	newattr "$comment" = "8 Bit Magnitude Comparator, 20k PullUp" ;
	newattr "$ttlout" = "TP" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q")
	  to ( 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19,     1) ;
	}

part 74ls683 : default so20,dil20 {
	newattr "$comment" = "8 Bit Magnitude Comparator, 20k PullUp" ;
	newattr "$ttlout" = "OC" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q")
	  to ( 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19,     1) ;
	}

part 74ls684 : default so20,dil20 {
	newattr "$comment" = "8 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "TS" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q")
	  to ( 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19,     1) ;
	}

part 74ls685 : default so20,dil20 {
	newattr "$comment" = "8 Bit Magnitude Comparator" ;
	newattr "$ttlout" = "OC" ;
	pin (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q","/p>q")
	  to ( 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19,     1) ;
	}

part 74ls686 : default so24,dil24,dil24b {
	newattr "$comment" = "8 Bit Magnitude Comparator, Out Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (/g1,/g2,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q",
	     "/p>q") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g1,/g2,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q",
	      "/p>q")
	  to (  2, 23, 3, 5, 8,10,13,15,17,20, 4, 6, 9,11,14,16,18,21,    22,
	           1) ;
	}

part 74ls687 : default so24,dil24,dil24b {
	newattr "$comment" = "8 Bit Magnitude Comparator, Out Enable" ;
	newattr "$ttlout" = "OC" ;
	pin (/g1,/g2,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q",
	     "/p>q") ;
	net "vss" : (12) ;
	net "vcc" : (24) ;
	xlat (/g1,/g2,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q",
	      "/p>q")
	  to (  2, 23, 3, 5, 8,10,13,15,17,20, 4, 6, 9,11,14,16,18,21,    22,
	           1) ;
	}

part 74ls688 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator, Output Enable" ;
	newattr "$ttlout" = "TP" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),
	        (11,12),(13,14),(15,16),(17,18),19) ] ) ;
	}

part 74ls689 : default so20,dil20 {
	newattr "$comment" = "8 Bit Identity Comparator, Output Enable" ;
	newattr "$ttlout" = "OC" ;
	pin (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q") ;
	net "vss" : (10) ;
	net "vcc" : (20) ;
	xlat (/g,p0,p1,p2,p3,p4,p5,p6,p7,q0,q1,q2,q3,q4,q5,q6,q7,"/p=q")
	  to ( 1, 2, 4, 6, 8,11,13,15,17, 3, 5, 7, 9,12,14,16,18,    19) ;
	swap ( [  1,
	       (( 2, 3),( 4, 5),( 6, 7),( 8, 9),
	        (11,12),(13,14),(15,16),(17,18),19) ] ) ;
	}

/*______________________________________________________________*/
/* Logical Library definition file end */

end.